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The Dark Silicon Problem and What It Means for CPU Designers (2013)

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Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#51

Post by deaddodo »

deepnotderp wrote: post #19
blackflame7000 wrote: post #2

Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall. Seems to me more internal volume might allow for more cleaver head distribution channels

1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance* 2. Power delivery is now ~n times worse where n is your transistor layer count. * 3. Connections between chips are very slow, power hungry and expensive. Fabrication of "monolithic" 3D is temperature wise painful and usually results in crummier transistors. With that being said, innov…

They do use some 3D techniques inside dies. Tri-gate transistors and 3DICs, for insurance

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#52

Post by perl4ever »

perl4ever wrote: post #28
wongarsu wrote: post #18

Earlier quoted context omitted.

For heat dissipation you want the most surface area per volume (because you can only transfer heat away in the surface area). The optimal arrangement for that would be a huge, flat, one atom thick surface. Another goal we have is low latency (and high clock rate, which is depenend on low latency), which suggests putting everything in a qube or even a shere. So we compromise somewhere in the middle with a square with…

"For heat dissipation you want the most surface area per volume (because you can only transfer heat away in the surface area). The optimal arrangement for that would be a huge, flat, one atom thick surface." Made me think of this: https://en.wikipedia.org/wiki/Menger_sponge Say we have roughly 300 sq mm, that's about 17.32 mm square, which is 8.24e+7 silicon atoms (0.21 nm) across. Then we have a surface area of roug…

Re "I suppose this isn't nearly as good as 4e10 flat sheets with 1 atom separation between each" - I guess it should be better, actually, now that I happened to notice 10+16 < 28. I got confused about whether my reference point was the basic cube or the flat sheet.

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#53

Post by deepnotderp »

deaddodo wrote: post #51
deepnotderp wrote: post #19

Earlier quoted context omitted.

1. Heat dissipation is now ~n x m times worse where n is your transistor layer count. And where m is the increased thermal resistance* 2. Power delivery is now ~n times worse where n is your transistor layer count. * 3. Connections between chips are very slow, power hungry and expensive. Fabrication of "monolithic" 3D is temperature wise painful and usually results in crummier transistors. With that being said, innov…

They do use some 3D techniques inside dies. Tri-gate transistors and 3DICs, for insurance

Yes well FinFETs and other non planar transistors are very different from what's being discussed here. Interestingly, FinFETs actually do suffer from a bit of a self heating effect although this usually isn't a problem for AC operation.

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#55

Post by deepnotderp »

wolfgke wrote: post #33
blackflame7000 wrote: post #2

Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall. Seems to me more internal volume might allow for more cleaver head distribution channels

> Why don't they start making CPUs 3 Dimensional like a cube with 6 "processors" each with multiple cores as its "sides" with the pins on the opposite sides of the cube wall. Not directly an answer to this specific question, but a (somewhat) colleague who writes his PhD thesis about 3-dimensional chip design made a popular scientific lecture about this topic. As I understood it, the central problem is that it is very…

Fun fact: the through silicon via was invented by William Shockley himself

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#56

Post by zaarn »

Phillipharryt wrote: post #7

From the article "The heat generation per unit area of an integrated circuit passed the surface of a 100-watt light bulb in the mid 1990s, and now is somewhere between the inside of a nuclear reactor and the surface of a star. " I can't tell if this is hyperbole or not, it amazes me but no amount of googling is coming up with a useful answer. Is anyone able to confirm or deny it for me?

Intel's latest CPU innovation, the i9 "Industrial Cooling Required" Edition with 28 cores, would come close to a nuclear reactor and does manage to replicate the heat output usually experienced during atmospheric reentry from orbit.

I doubt it comes close to the surface of the average star but certainly close to some of the cooler red dwarf stars and probably most brown dwarf stars.

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#57

Post by JudasGoat »

The author states "For every watt of power the CPU consumes, it must dissipate a watt of heat." It was always my understanding that that in electrical devices, (with the exception of heaters) the amount of heat produced was inversely proportional to the efficiency of the device. So is it really true that all energy provided to the CPU or SOC is dissapated as heat?

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#58

Post by agumonkey »

deepnotderp wrote: post #54
agumonkey wrote: post #50

Earlier quoted context omitted.

What about stacked heat vias ?

What are those? Do you mean something like thermal "dummy" vias?

yeah, something imprinted in all layers so you could evacuate heat

Re: The Dark Silicon Problem and What It Means for CPU Designers (2013)

#59

Post by Elrac »

JudasGoat wrote: post #57

The author states "For every watt of power the CPU consumes, it must dissipate a watt of heat." It was always my understanding that that in electrical devices, (with the exception of heaters) the amount of heat produced was inversely proportional to the efficiency of the device. So is it really true that all energy provided to the CPU or SOC is dissapated as heat?

The author's sentence is essentially a truism, because fiddling with information _as such_ and in theory doesn't use up any energy. As practically implemented in current CPU electronics, though, information needs to be communicated from point A to point B as a change in voltage. To convey that voltage change means having to move some amount of electrical charge into or out of the tiny capacitor that is a transistor's gate, via the non-perfect conductor that is the doped-silicon trace between the two points. Resistance saps part of the energy moving those electrons around and converts it to heat.
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