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Darpa invests $100M in a silicon compiler

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Re: Darpa invests $100M in a silicon compiler

#151

Post by 437598735 »

On the opposite side of the spectrum, there's Chuck Moore (Forth creator) who in trying to find the simplest combination of software and hardware for his projects devoted a lot of time into a DIY VLSI CAD system. Fascinating history behind it, although the actual OKAD system is essentially trade secret for his company.

His site has been down for a while, but someone thankfully mirrored most of the pages here: https://colorforth.github.io/vlsi.html

More history about OKAD, plus links to more about Forth both software and hardware: http://www.ultratechnology.com/okad.htm

Re: Darpa invests $100M in a silicon compiler

#152

Post by civilitty »

slededit wrote: post #112
civilitty wrote: post #90

Earlier quoted context omitted.

With this you can do 0.5mm pitch BGA although that is pushing it. If you have actually figured out how to consistently make boards with BGA-256/512 0.5mm pitch parts with just a toaster, I'd love to learn more about your technique. Even with professional inspection equipment and a pick and place, it's rarely worth the effort unless I have an imminent deadline. For a beginner, I doubt the cost of trial and error would…

I use a 10x jewelers microscope and tweezers to get the alignment perfect. The hardest part is actually applying the solder paste there is no room for registration errors. I triple check everything. As for the reflow profile I raise the temperature gradually, with the thermocouple taped directly to the PCB with kapton tape. I do this manually, not with an automatic controller. My toaster oven is a convection model wi…

My appologies, I work largely on client/personal projects in the high speed digital/RF domain so my assumptions can be all over the place. Client budgets/deadlines leave little room for mistakes and my dexterity isn't what it once was so I use a PNP or make funky assembly jigs (my CV implementation/hands makes it easier to align with pins).

If you can, I'd really recommend talking to dentists who are retiring in your area or buying an XRay machine on ebay. They're pretty cheap and relatively safe and will open up a whole world of PCB fab. The problem with BGAs is the lack of feedback: if you have a chip with hundreds of pins and precise requirements for power boot up timing or dozens of impedance matched traces, figuring out what went wrong with your boards is literally impossible without proper inspection.

Since you have an intuitive feel for soldering BGAs already, I think that with a visualization of the solder joints you would be able to solder high pin count chips at small pitches. Most issues that I've experienced with complex BGAs are caused by mass manufacturing where you dont have the room to reflow every 10th board and you find out too late that a variable (from personal experience: el nino) has changed and reduced your yields by double digits. If you can take the time to do it right by hand, the sky's the limit.

If your back is against the wall you can also hotfix design mistakes like swapping two LVDS MIPI2 pins by using a laser drill to strip the plating on microvias at an angle to preserve the trace above it and resoldering them with wire only slightly bigger than IC interconnects. An almost completely useless skill but nothing beats the feeling you get when you can command RoHS compliant surface tension to do your bidding. Fair warning though: here be dragons.

Re: Darpa invests $100M in a silicon compiler

#153

Post by kevin_thibedeau »

WalterBright wrote: post #77
ur-whale wrote: post #14

"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…

I designed the ABEL language back in the 80's for compiling designs targeted at programmable logic arrays and gate arrays. It was very successful, but it died after a decade or so. It'd probably be around today and up to date if it was open source. A shame it isn't. I don't even know who owns the rights to it these days, or if whoever owns it even knows they have the rights to it, due to spinoffs and mergers.

Xilinx supported their flavor until ISE 10 which is still available to download. They also had a code converter to the HDLs so you could still theoretically target the latest FPGAs using ABEL with some scripting to orchestrate the mixed tooling.

Re: Darpa invests $100M in a silicon compiler

#154

Post by slededit »

civilitty wrote: post #152
slededit wrote: post #112

Earlier quoted context omitted.

I use a 10x jewelers microscope and tweezers to get the alignment perfect. The hardest part is actually applying the solder paste there is no room for registration errors. I triple check everything. As for the reflow profile I raise the temperature gradually, with the thermocouple taped directly to the PCB with kapton tape. I do this manually, not with an automatic controller. My toaster oven is a convection model wi…

My appologies, I work largely on client/personal projects in the high speed digital/RF domain so my assumptions can be all over the place. Client budgets/deadlines leave little room for mistakes and my dexterity isn't what it once was so I use a PNP or make funky assembly jigs (my CV implementation/hands makes it easier to align with pins). If you can, I'd really recommend talking to dentists who are retiring in your…

I've noticed it a lot going to trade shows that the North American market has turned so much to the high end that most people assume you need all this fancy gear to make anything. Its really stifling innovation in my opinion. People think they needs tens of thousands to get an MVP prototype out the door and most of the time it kills the idea. If you are a big company and already have the resources then by all means use them, but someone with a good idea shouldn't think its required to build something new.

On the high speed digital front we do have 1Ghz DDR3 and its worked very well - we don't even use controlled impedance. Of course we are extremely careful to keep traces short and length matched. Our application can handle a very small error rate, however in practice we haven't seen any corruption at all in testing.

Its not the right approach if you are pushing the envelope of technology. But if you need a bit more grunt than an atmega by all means design in the ARM SoC and DDR3. You don't need fancy gear to do it.

Edit: Also thanks, we're looking into expanding more manufacturing in house and you've given me some ideas. I'll definitely look into an XRay machine.

Re: Darpa invests $100M in a silicon compiler

#156

Post by civilitty »

ethbro wrote: post #147
emeraldd wrote: post #126

Earlier quoted context omitted.

Or their hardware, some of the impact of those bugs could be built into the physical hardware. By that point. Edit:fixed a typo.

Add in qualification of specific hardware inside specific operating conditions. The "move stuff and break stuff" crowd forgets there's a market for "move slow and rarely break stuff" too. So if you have qualified hardware w/ a certain driver version, you don't just ship a bunch of code fixes to a customer, you ship the bare minimum change set required to fix any specific issues they experience. Because you're sure as…

I am definitely not one of those "move fast and break stuff" people, especially since I often have only a few months to design something that is expected to be in service until oxidation is a legitimate concern. My personal ventures are largely web based so I've also become rather too personally acquainted with the other extreme - the madness that is node_modules/, implicit *.d.ts imports, and browser impedance mismatches.

The problem in the hardware industry is far more insidious. Unlike with software dev, there is no concept of "full stack" or "devops" in manufacturing. The entire field is so hyperspecialized that youve got people dedicated to tuning reflow temperatures to +-5C depending on humidity and local weather. No one person can have a proper big picture view of the situation so the entire industry is dominated by silos each with their own micro-incentives and employees competing with each other for notoriety.

Re: Darpa invests $100M in a silicon compiler

#157

Post by analognoise »

alexbeloi wrote: post #20

A great blog post here ( https://wp.josh.com/2017/10/23/adventures-in-autorouting/ ) about some different auto-routing software.

Those routes look terrible. Maybe if everything you're doing is electrically short and there are no high speed routes, it would work great. Basically it's wonderful if all you make are blinkenlight projects.

But if you have to input all of the data that makes up a good route (including coupling, ground/power planes, trace length matching, PDN noise, stackup, EMI/C rules, etc, etc), and then review the whole thing anyway, what's the point of the autorouter?

Also the article says nothing about the various algorithms involved, which are interesting from a computational geometry standpoint. But the gulf between algorithm or academic example and "commercial router" is huge!

This blog post is just... not very good. It's how I imagine a software person who made some stupid blinky LED thing thinks about hardware.

Re: Darpa invests $100M in a silicon compiler

#158

Post by eximius »

fjsolwmv wrote: post #143
taneq wrote: post #133

Earlier quoted context omitted.

I think there's also liability issues, like if they give away food and someone gets salmonella poisoning or has an allergic reaction or something then they could get sued. It sucks but it's not completely arbitrary.

That's a myth. Good Samaritan laws exempt that

Doesn't get rid of bad press.

Re: Darpa invests $100M in a silicon compiler

#159

Post by seattleeng »

WalterBright wrote: post #77
ur-whale wrote: post #14

"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…

I designed the ABEL language back in the 80's for compiling designs targeted at programmable logic arrays and gate arrays. It was very successful, but it died after a decade or so. It'd probably be around today and up to date if it was open source. A shame it isn't. I don't even know who owns the rights to it these days, or if whoever owns it even knows they have the rights to it, due to spinoffs and mergers.

I think you'd be surprised. I went to Caltech (graduated 2014), which is a fairly well known university for their Electrical Engineering program, and I learned ABEL in my Sophomore/Junior year. My instructor, an admittedly old school hardware engineer, was in love with the language and had it as part of our upper level digital design curriculum for a few labs. FWIW, I think it was super intuitive and a hugely valuable learning tool. I suppose that doesn't mean it isn't "dead" for professional purposes, though.

Re: Darpa invests $100M in a silicon compiler

#160

Post by seattleeng »

drblast wrote: post #128
WalterBright wrote: post #77

Earlier quoted context omitted.

I designed the ABEL language back in the 80's for compiling designs targeted at programmable logic arrays and gate arrays. It was very successful, but it died after a decade or so. It'd probably be around today and up to date if it was open source. A shame it isn't. I don't even know who owns the rights to it these days, or if whoever owns it even knows they have the rights to it, due to spinoffs and mergers.

Holy shit, around 2005/6 I took an EE class in programmable logic that used ABEL for the labs. I couldn't find any information on it anywhere and all we had to learn the language was an old single-page photocopy of an example that had been re-copied so many times it was barely readable. And the ends of the lines were cut off. Needless to say, the ABEL projects were frustrating...indeed a shame that it's not open sour…

Did you go to Caltech by any chance?
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