Darpa invests $100M in a silicon compiler • Hacker News Board

Re: Darpa invests $100M in a silicon compiler

#111

Post by rixrax » Sat, Jun 30, 2018, 1:29 AM UTC

ur-whale wrote: post #62

rixrax wrote: post #49

Earlier quoted context omitted.

>> "Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " I'll have popcorn ready for the eventuality where IP blocks are widely available under GPL type of FOSS licenses and Intel|AMD|ARM|TI|... is eventually found to include one or more of those open sourced blocks with incompatible license in their chips.

The exact same arguments have been perused ad nauseam by old-timers in the software industry in the 80's and 90's when they clamored against open-source being anti-capitalist and un-american. Not sure how and why H/W is different.

I was thinking this mostly from the standpoint of viral nature of GPL-kind of FOSS licenses. E.g. somehow, somewhere someone manages to inject a GPL licensed IP block into a commercial CPU, after which, with my layman understanding, chip manufacturer now owes under the terms of GPL everyone who happens to have purchased one of those chips a full VHDL, Verilog etc. source code of the entire chip.

In software you can always replace a library that had incompatible license with another. Not sure how this would work with a chip.

As for attempts to modernize EDA industry, I welcome that in open arms. And if in the process we end up open sourcing a lot of current IP blocks (think of USB, HDMI, etc. designs) - all the better.

Re: Darpa invests $100M in a silicon compiler

#112

Post by slededit » Sat, Jun 30, 2018, 1:29 AM UTC

civilitty wrote: post #90

slededit wrote: post #73

Earlier quoted context omitted.

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way. The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB…

With this you can do 0.5mm pitch BGA although that is pushing it. If you have actually figured out how to consistently make boards with BGA-256/512 0.5mm pitch parts with just a toaster, I'd love to learn more about your technique. Even with professional inspection equipment and a pick and place, it's rarely worth the effort unless I have an imminent deadline. For a beginner, I doubt the cost of trial and error would…

I use a 10x jewelers microscope and tweezers to get the alignment perfect. The hardest part is actually applying the solder paste there is no room for registration errors. I triple check everything.

As for the reflow profile I raise the temperature gradually, with the thermocouple taped directly to the PCB with kapton tape. I do this manually, not with an automatic controller. My toaster oven is a convection model with a fan which helps, and I had some trial and error with the rack position.

The part in question is: TPS62180 which is a dual phase step down converter.

Edit: I think you are conflating I've done both high ball count and 0.5mm. Never both at the same time. I've soldered high ball count Xilinx FPGAs at 0.8mm which was relatively easy. Also I stress these are for prototypes. You can do production runs and that is how the company behind 3DRobotics got their start in the early days of quadrotors but its a whole other ball of wax.

Re: Darpa invests $100M in a silicon compiler

#113

Post by makmanalp » Sat, Jun 30, 2018, 1:32 AM UTC

civilitty wrote: post #53

ur-whale wrote: post #14

"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…

It's not just the EDA industry, it's almost all of hardware including most of the embedded software people. Yeah, I get it - I too am sometimes stuck using some old proprietary compiler with a C standard older than some of the people I work with - but come on. On my last job I used a Qualcomm radio and they ended up giving me close to a thousand zip files of driver revisions going back a decade because their build pr…

> the backoffice engineers would make a build that fixed only those bugs

Makes perfect business sense! Those customers didn't pay to get those bugs fixed, so why should they get the fixes??? /s

Holy moly.

Re: Darpa invests $100M in a silicon compiler

#114

Post by seanmcdirmid » Sat, Jun 30, 2018, 1:34 AM UTC

wcrichton wrote: post #30

My advisor at Stanford is working on an open-source hardware toolchain to solve these exact problems. The Agile Hardware Center is trying to bring software methodologies of rapid prototyping and pervasive code sharing/reuse to ASICs, CGRAs, and FPGAs: https://aha.stanford.edu/

It’s a bit ironic that a decade or two ago, there was a drive to make software development look more like hardware development (as if it were somehow better), but the trend has swung all the way around.

Re: Darpa invests $100M in a silicon compiler

#115

Post by magila » Sat, Jun 30, 2018, 1:46 AM UTC

typon wrote: post #70

JumpCrisscross wrote: post #5

Side note: when people complain about the military budget, projects like these should be noted. Political reality in America, today, is military R&D and jobs programs are easier to fund than civilian ones; so that’s where projects go to live.

So instead of explicitly funding research we should implicitly fund it in a roundabout way and you're saying people shouldn't complain about this state of things?

I have seen many people on HN and elsewhere use the same argument in other contexts. For example, to justify spending on the Apollo program on the grounds that some of the money was used to fund research which turned out to be useful outside of manned space flight. So apparently it is indeed considered a perfectly fine state of affairs.

I'm being a bit facetious of course, I just find it funny that people's acceptance of this argument depends on how much they support the primary subject of the funding.

Re: Darpa invests $100M in a silicon compiler

#116

Post by ghettoimp » Sat, Jun 30, 2018, 1:47 AM UTC

ur-whale wrote: post #29

darzu wrote: post #21

Earlier quoted context omitted.

They have. The problem is that efficient silicon layout is NP-complete and automated tools can't do better than humans today. At best they can assist and detect certain classes of errors. I'm sure Intel has invested more than $100 million on tooling by now.

There are many NP complete problems where computer do vastly better than humans. But when it comes to EDA, the utterly closed-source culture of the industry has completely prevented what essentially amounts to a horde of smart people to work on the problem: no one - except a very small number insiders - even know what the problems are.

It's really godawful. Software guys have no idea how good they have it.

You have layers upon layers of closed source EDA tools and home-brew scripts, all built around horribly abysmal "standards" like SystemVerilog, mostly cobbled together in TCL and Perl.

For instance, the following sounds like a horrible joke, but it is real. In a real life, world-class company, port connections between modules are handled using a Perl script. This perl script invokes, I shit you not, an Emacs-Lisp Verilog parser, that scans your files to figure out what submodules you are instantiating, infers the ports that you want to connect, then injects a blob of connections directly into the source code file you were editing. The engineers at this company then commit the output of this Perl script into their source code repository. Predictably the diffs are full of line noise.

And you can't escape from this, any of it, because there are so many tools involved, and they all do such useful things, that you end up truly stuck using whatever features all of the tools support. And `ifdefs. Sigh...

Re: Darpa invests $100M in a silicon compiler

#117

Post by namibj » Sat, Jun 30, 2018, 1:52 AM UTC

xt00 wrote: post #95

adrianmonk wrote: post #12

So it costs $500 million every time someone designs a SoC and (before now) nobody has spent $100 million trying to make that more efficient?

I think the primary focus / value here would be if they can somehow dramatically reduce the cost of making masks and IC's. Lets say these researchers make the actual process of converting C code to silicon super easy, then you go to make the chip and they are like, "cool, the mask / fab cost is like 500k USD for samples" -- then basically the exact same people who currently make chips will keep making chips. What wou…

Uh, for 90nm you should be in the 4-digit range for a hand full of prototypes.

Re: Darpa invests $100M in a silicon compiler

#118

Post by analognoise » Sat, Jun 30, 2018, 1:54 AM UTC

WalterBright wrote: post #77

ur-whale wrote: post #14

"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…

I designed the ABEL language back in the 80's for compiling designs targeted at programmable logic arrays and gate arrays. It was very successful, but it died after a decade or so. It'd probably be around today and up to date if it was open source. A shame it isn't. I don't even know who owns the rights to it these days, or if whoever owns it even knows they have the rights to it, due to spinoffs and mergers.

Verilog was heavily influenced by ABEL, and is now the predominant HDL in many places.

Re: Darpa invests $100M in a silicon compiler

#119

Post by analognoise » Sat, Jun 30, 2018, 1:56 AM UTC

rixrax wrote: post #49

ur-whale wrote: post #14

"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…

>> "Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " I'll have popcorn ready for the eventuality where IP blocks are widely available under GPL type of FOSS licenses and Intel|AMD|ARM|TI|... is eventually found to include one or more of those open sourced blocks with incompatible license in their chips.

This will never, ever happen, so why ponder it?

Re: Darpa invests $100M in a silicon compiler

#120

Post by usmannk » Sat, Jun 30, 2018, 2:06 AM UTC

makmanalp wrote: post #113

civilitty wrote: post #53

Earlier quoted context omitted.

It's not just the EDA industry, it's almost all of hardware including most of the embedded software people. Yeah, I get it - I too am sometimes stuck using some old proprietary compiler with a C standard older than some of the people I work with - but come on. On my last job I used a Qualcomm radio and they ended up giving me close to a thousand zip files of driver revisions going back a decade because their build pr…

> the backoffice engineers would make a build that fixed only those bugs Makes perfect business sense! Those customers didn't pay to get those bugs fixed, so why should they get the fixes??? /s Holy moly.

I think a reasonable explanation may be that other customers possibly have come to unknowingly rely on some of the bugs. Shipping a fix of all the bugs could actually break their code!