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AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

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Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#41

Post by wolf550e »

jostmey wrote: post #37
dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

Writing code to run in parallel across a large number of small "chips" is probably the future of programming. In this sense, new programming languages like Julia might prove useful?

This "future of programming" was very widely announced in 2005: http://www.gotw.ca/publications/concurrency-ddj.htm

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#42

Post by kdmytro »

zitterbewegung wrote: post #17
digi_owl wrote: post #14

Earlier quoted context omitted.

Sounds somewhat similar to what Intel started offering recently, in collaboration with AMD. Basically a Intel CPU and an AMD GPU in a single package, for use in laptops that needed something beefier than an Intel GPU but didn't have the volume allowance for a full GPU card.

They also have a budget Ryzen that does the same thing but with their own Vega graphics. I am using one now for web development and distributed ledger development.

> ... and distributed ledger development.

You are careful not to say "blockchain" :)

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#43

Post by insulanus »

wolf550e wrote: post #41
jostmey wrote: post #37

Earlier quoted context omitted.

Writing code to run in parallel across a large number of small "chips" is probably the future of programming. In this sense, new programming languages like Julia might prove useful?

This "future of programming" was very widely announced in 2005: http://www.gotw.ca/publications/concurrency-ddj.htm

Yes, and in the 90s https://en.wikipedia.org/wiki/Thinking_Machines_Corporation

And the 80s https://en.wikipedia.org/wiki/Transputer

And, aw heck. We knew it was coming :) https://en.wikipedia.org/wiki/History_of_supercomputing

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#44

Post by faragon »

"The AMD team found that deadlocks on active interposers basically disappear if you follow a few simple rules when designing on-chip networks"

I would like to know how they solved that problem. Is there any public paper or patent explaining that?

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#45

Post by frozenport »

Quequau wrote: post #35
greglindahl wrote: post #33

Earlier quoted context omitted.

Check out Intel Omni-Path, it's a separate chip on-package for Intel's high end cpus. 100 gigabit network.

I can't afford Intel's high-end stuff. That's why I'm looking at AMD.

Really the network is the least expensive part. To get IO that can saturate a 10G costs around 20k, while the infiniband card sets you back less than 4k. Now you're talking about 100G, which will go faster, you could easily be looking at a 500k box of ssds.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#46

Post by CuriousCosmic »

kdmytro wrote: post #42
zitterbewegung wrote: post #17

Earlier quoted context omitted.

They also have a budget Ryzen that does the same thing but with their own Vega graphics. I am using one now for web development and distributed ledger development.

> ... and distributed ledger development. You are careful not to say "blockchain" :)

Just because something is a distributed ledger does not necessarily mean it is a blockchain.

Yes, they are a dev in the cryptocurrency/blockchain space but still, who knows?

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#47

Post by BooneJS »

In the beginning, a sea of discrete components made up a system. Investment in fab technology caused process nodes to shrink very 18 months so these discrete components gave way to the System-On-Chip where the board of chips was replaced by a single chip.

Now physics is harder to overcome, the cost of development at the bleeding edge of technology is higher than ever, and the continued desire for larger and larger systems caused the SoC to break apart again. It’ll be interesting to see if this is what the future looks like for silicon-based chips, or if this is a temporary shortcut.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#48

Post by paulmd »

dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

> The advantage for AMD is that they've built a single design: the Zeppelin die. RyZen is simply one Zeppelin. Threadripper is two Zeppelins. And EPYC is four Zeppelins.

While a popular meme, this is not actually true. Epyc is actually a totally different die, stepping B2 vs the B1 die used in Ryzen+TR.

https://en.wikichip.org/wiki/amd/ryzen_7/1800x

https://en.wikichip.org/wiki/amd/epyc/7601

The 2700X is actually on a different die as well, and Raven Ridge on another. There will probably be another die for Banded Kestrel, if AMD ever gets around to releasing that. Presumably, their embedded SOC products are their own die as well.

So, about 5 dies per generation, across AMD's lineup (Epyc, Ryzen, APU, Atom, and embedded SOC). They're using about half as many dies as Intel is - still a significant difference, but far from the "one die for the whole lineup!" meme.

The big difference is that they're serving the whole server market with one small die, vs the three that Intel uses.

Of course, a small die isn't all roses either - both mfrs limit you to 8 dies per system, so right now with an 8-core die AMD systems are limited to 64-core systems (dual-socket Epyc) versus the 224-core systems that you can do with octo-socket 28-core Xeons. But, not everybody needs a million-dollar octo-socket system either.

Once AMD takes a node advantage that advantage will be diminished somewhat, but Intel's 10nm woes are a whole different story ;)

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#49

Post by dragontamer »

BooneJS wrote: post #47

In the beginning, a sea of discrete components made up a system. Investment in fab technology caused process nodes to shrink very 18 months so these discrete components gave way to the System-On-Chip where the board of chips was replaced by a single chip. Now physics is harder to overcome, the cost of development at the bleeding edge of technology is higher than ever, and the continued desire for larger and larger sy…

I'm not sure if SoC is breaking apart actually. I think chipbuilders are figuring out that its more efficient to combine some dies together at the package level.

Consider that EPYC is basically a miniturized multi-socket design. Infinity Fabric is really AMD's new protocol built on top of HyperTransport (multi-socket protocol from the past). Before, AMD used to support 8-sockets. But today, AMD stitches 4-chips together and only supports 2-sockets.

From a software perspective (ie: NUMA), EPYC x2 sockets looks like an 8-socket chip of old. In effect, AMD has miniturized the 4x-socket setup in the form of EPYC. And it has also miniturized the 2x socket setup in the form of Threadripper.

----------------------

These Threadripper / EPYC chips have the same downsides as all old 2x, 4x, and 8x NUMA designs of the past. High latency and poor communications between cores.

The thing is: the modern environment is a highly virtualized, highly independent set of systems. Running 8x NUMA efficiently today is as simple as spinning up 8x VMs, one for each NUMA node.

IIRC, people are finding that Intel's 28-core design is far more effective in say... unified Database performance. Intel's design has a true L3 cache which can be used by all 28-cores, while AMD's L3 cache is split between each die. 4x 8MB caches cannot function as a singular cache in a large-scale database application.

But there's enough situations (ie: VMs, multitasking, render farms) where AMD's NUMA + Infinity Fabric is good enough. And with prices anywhere from 1/4th to 1/2 the cost of Intel, AMD's chips these days are certainly worth considering.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#50

Post by namibj »

digi_owl wrote: post #20
zitterbewegung wrote: post #17

Earlier quoted context omitted.

They also have a budget Ryzen that does the same thing but with their own Vega graphics. I am using one now for web development and distributed ledger development.

I figured those where made much like their APUs of previous years, meaning that it was all on a single die.

You are correct. Look at wikichip for details.
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