Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors • Hacker News Board

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#111

Post by perl4ever » Mon, May 21, 2018, 3:58 AM UTC

SlowRobotAhead wrote: post #107

ktta wrote: post #89

Earlier quoted context omitted.

There's no need for all caps. HDL can be referred to as code. And I do know what HDL is and what FPGAs are, thank you.

>HDL can be referred to as code. No, it can't. That's why the caps are there and I'm sticking to it. You basically justified it ;) Code is something that you design to run sequentially. HDL is a description of gates and logic that runs all at the same time. If you wanted to argue that the bitstream is firmware - that's a tougher discussion.

If code is inherently sequential, do you think that there is no such thing as "code" in functional programming languages?

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#112

Post by krupan » Mon, May 21, 2018, 5:32 PM UTC

craigjb wrote: post #71

obl wrote: post #8

Earlier quoted context omitted.

HDLs are fine. I've found the tooling around them to be quite atrocious (slow, buggy, opaque, gui-based) though. Be it for synthesis, simulation, or even just compiler errors it's pretty bad compared to software.

I’ve started using SpinalHDL, https://github.com/SpinalHDL/SpinalHDL . It’s a Scala DSL that spits out Verilog or VHDL for traditional synthesis tools. But, unlike Chisel or MyHDL, in my opinion it’s a great experience. And, now it has seamless integration with Verilator for simulation, and the open-source Verilator project is very capable—they claim it beats commercial simulators: https://www.veripool.org/wiki/veril…

Are you writing your testbench code in C++? (that's what verilator wants, isn't it?)

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#113

Post by tfmkevin » Fri, May 25, 2018, 6:20 PM UTC

slivym wrote: post #96

agumonkey wrote: post #83

Earlier quoted context omitted.

I don't know how fast the FPGA can reconfigure itself or part of it, but you could also have per process bare metal JIT

It takes in the order of seconds to reconfigure. JIT is not really viable.

Nope. Reconfiguration takes milliseconds. Also, Arria 10 supports partial reconfiguration which means that the FPGA can keep operating while some of the logic is reconfigured via bitstream.