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Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

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Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#101

Post by clouddrover »

slivym wrote: post #94
srum wrote: post #93

Earlier quoted context omitted.

I'm not even sure they're going to let you program the FPGA drectly (with HDL)? I expect the main workflow will be using OpenCL to offload arbitrary work to the coprocessor along with a few Intel-provided modules capable of common tasks. The great thing about having the FPGA on-die via UPI is that the cache-coherency, decreased latency and massive bandwidth will allow much more granular offloading of work. This is as…

Using OpenCL to program an FPGA is a significantly more difficult task than programming in HDL. Atleast for what would be relevant to a Xeon co-processor. The OpenCL flow is just terrible at getting to the performance levels you need to realistically offload anything from a Xeon. Intel are certainly working on it, but that's not a realistic proposition for the next 5 years, and if the Xeon+FPGA isn't already successf…

Video encoding would be another good application for the FPGA.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#102

Post by agumonkey »

slivym wrote: post #96
agumonkey wrote: post #83

Earlier quoted context omitted.

I don't know how fast the FPGA can reconfigure itself or part of it, but you could also have per process bare metal JIT

It takes in the order of seconds to reconfigure. JIT is not really viable.

we need to jit the fpga jit jit then

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#103

Post by virtuallynathan »

slivym wrote: post #97

What I'm really interested to know is how this looks from a power-performance perspective. An Arria 10 can draw 20-40 watts (I'm not sure that 90w is really realistic), and the TDP for the Xeon is 165W. When I saw the discussion about this in the past with people who work at Intel the discussion wasn't 165+90 = 225TDP. It was actually "Oh so you want to use the FPGA, better turn off 6 of those Xeon cores! That could…

Intel Scalable CPUs are already at 205W TDP, and also see: https://en.wikichip.org/wiki/intel/xeon_platinum/8124

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#104

Post by slivym »

clouddrover wrote: post #101
slivym wrote: post #94

Earlier quoted context omitted.

Using OpenCL to program an FPGA is a significantly more difficult task than programming in HDL. Atleast for what would be relevant to a Xeon co-processor. The OpenCL flow is just terrible at getting to the performance levels you need to realistically offload anything from a Xeon. Intel are certainly working on it, but that's not a realistic proposition for the next 5 years, and if the Xeon+FPGA isn't already successf…

Video encoding would be another good application for the FPGA.

I'm not so sure - it's a fantastic fit for GPUs, FPGAs make sense for stream processing for video encoding - but that's more of a discrete device play where you can plug the video feeds directly into the FPGA daughter board.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#105

Post by slivym »

ktta wrote: post #29
duskwuff wrote: post #12

Earlier quoted context omitted.

Intel/Altera has HLS tools as well: https://www.altera.com/products/design-software/high-level-d...

Well there you go. So GP's concerns are largely addressed. Intel can just work on this tooling, and people who are going to use HDL are going to continue using them.

Good idea in theory, in practice it's a shit show. The current level of language support is "As long as you know how to write what you want in HDL, then you can write some C that uses custom pragmas and design patterns and attributes that will badly reproduce what you could have written in HDL in half the time".

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#106

Post by monocasa »

phendrenad2 wrote: post #65
monocasa wrote: post #33

Earlier quoted context omitted.

Wow, someone managed to make something even worse than the "compile your C to an FPGA" tools you see occasionally. The model is just too different for these things to make sense 99% of the time. It's like trying to run general purpose code on a GPU, but even worse.

Wait until you see the python-to-FPGA tool :P

This one does that thanks to IronPython, lol.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#107

Post by SlowRobotAhead »

ktta wrote: post #89
SlowRobotAhead wrote: post #77

Earlier quoted context omitted.

HDL ISNT CODE. FPGAs don’t get firmware. HDL is a description of hardware.

There's no need for all caps. HDL can be referred to as code. And I do know what HDL is and what FPGAs are, thank you.

>HDL can be referred to as code.

No, it can't. That's why the caps are there and I'm sticking to it. You basically justified it ;)

Code is something that you design to run sequentially. HDL is a description of gates and logic that runs all at the same time.

If you wanted to argue that the bitstream is firmware - that's a tougher discussion.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#108

Post by monocasa »

mozumder wrote: post #80
SlowRobotAhead wrote: post #76

Earlier quoted context omitted.

Allow me to introduce myself... not really becsuse anoniminity. But I’m effectively an EE at my company with no degree. Hardware, firmware, software, sourcing, production, validation/testing, and low volume assembly, all self taught. I’ll grt into FPGA when I have a use for it, but it certainly won’t be FFTs and DSPs but still. I’m glad I don’t have to job surf, it would be hard without paper, but my experience would…

For sure technicians that do these are a thing for finishing work, who may have AS degrees instead of BS EE. I've worked with them as well. They were always referred to as technicians that EE's hand-off more of the board-level debugging to (or even GDS II for ASIC design..). The core datapath processing algorithms were always done by EE's, though.

I'm another one. Embedded Engineer, no degree, works on core datapath and high level design, in addition to debug work.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#109

Post by akhilcacharya »

bitcoinmoney wrote: post #58
akhilcacharya wrote: post #21

Earlier quoted context omitted.

How do you define "bank"?

I get paid 130k with a phd EE from tier 3 with <3 years industry experience. If you want to get in get ECE and study computer architecture and RTL. I am doing hardware modeling to predict future performance. It’s difficult to get in the industry from a tier 3 w/o experience but it’s worth it. My counterparts in FAANG are no doubt getting 300k/year. Sometimes I think maybe I should leetcode and get a software job @ FA…

all of my offers out of undergrad were more than that and I’m considered below average ¯\_(ツ)_/¯

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#110

Post by imtringued »

slrz wrote: post #15
ktta wrote: post #9

Earlier quoted context omitted.

I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx which is pretty much that. I'm not aware of Altera's current offerings but they won't overlook this so easily.

> I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. These (almost by necessity) make you write code that doesn't look like any other C code. You can't just use some pre-existing C library and compile it to use FPGA resources. At that point, why not go a step further and just use a proper HDL?

>At that point, why not go a step further and just use a proper HDL?

You're assuming that you're starting with an FPGA only project. In reality most projects that are going to be accellerated with these Xeon+FPGA systems is existing software where only a handful of hotspots will have be ported to the limited C language which is significantly less effort than rewriting the entire algorithm in HDL.

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