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Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

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Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#91

Post by bsder »

denkmoon wrote: post #51
jayonsoftware wrote: post #27

Earlier quoted context omitted.

Arria 10 FPGA is kind of mid range, I think they go around for 500 bucks , you can buy the dev board for 5K ( https://www.altera.com/products/boards_and_kits/dev-kits/alt... )

Why are dev boards that much more expensive in general? I can't believe that it costs 10x as much to "just" put the chip on a pcie board.

Um, the FPGA chip on that board retails for $10K according to findchips.com so ... (of course, anyone really ordering these class of chips is going to order them directly from Intel or Xilinx--but that doesn't mean the FPGA will be cheap)

Intel isn't making a lot of money on those boards if they aren't actually taking a loss.

1) A PCI-e board is non-trivial. It requires some engineer to sit down and do some serious signal integrity work.

2) A board with a fine-pitch BGA is non-trivial. These boards generally have via-in-pad and blind vias on the top two layers. The boards are also generally 8-12 layers.

3) The support circuitry on those boards in non-trivial. There's high-speed, fine pitch connectors that are probably in the $100 each range, themselves.

4) Really, you're paying for customer support. You will hit bugs. You will have to communicate with Intel. You probably won't order enough volume to make it worthwhile for Intel.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#92

Post by simias »

denkmoon wrote: post #51
jayonsoftware wrote: post #27

Earlier quoted context omitted.

Arria 10 FPGA is kind of mid range, I think they go around for 500 bucks , you can buy the dev board for 5K ( https://www.altera.com/products/boards_and_kits/dev-kits/alt... )

Why are dev boards that much more expensive in general? I can't believe that it costs 10x as much to "just" put the chip on a pcie board.

I have an Arria 10 SoC dev board (not the PCI one, the stand alone version). It's a very complex and fully featured board, it's just not just a "breakout board" for the FPGA. It's also clearly aimed at companies looking to integrate an Arria 10 into their designs, not hobbyists looking for a cheap FPGA board and the pricing reflects that.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#93

Post by srum »

kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

I'm not even sure they're going to let you program the FPGA drectly (with HDL)?

I expect the main workflow will be using OpenCL to offload arbitrary work to the coprocessor along with a few Intel-provided modules capable of common tasks.

The great thing about having the FPGA on-die via UPI is that the cache-coherency, decreased latency and massive bandwidth will allow much more granular offloading of work. This is as compared with PCIe coprocessor where it only makes sense to offload larger chunks of work and minimise the communication and data passing between the two.

The greater the granularity of work that we can offload, the more viable the OpenCL/high-level synthesis/heterogeneous computing type stuff will be, as it will integrate more seamlessly into existing software development methods. This is the holy grail at the moment for FGPA vendors: to get to the point where software developers can program them on their own.

As to your point though I guess we'll find out soon what the dev tools for this will actually look like.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#94

Post by slivym »

srum wrote: post #93
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

I'm not even sure they're going to let you program the FPGA drectly (with HDL)? I expect the main workflow will be using OpenCL to offload arbitrary work to the coprocessor along with a few Intel-provided modules capable of common tasks. The great thing about having the FPGA on-die via UPI is that the cache-coherency, decreased latency and massive bandwidth will allow much more granular offloading of work. This is as…

Using OpenCL to program an FPGA is a significantly more difficult task than programming in HDL. Atleast for what would be relevant to a Xeon co-processor. The OpenCL flow is just terrible at getting to the performance levels you need to realistically offload anything from a Xeon. Intel are certainly working on it, but that's not a realistic proposition for the next 5 years, and if the Xeon+FPGA isn't already successful in that time frame, it'll be canned long before OpenCL is a solution.

From what I've seen the only applications for this will be pre-canned FPGA images that were written in-house by Intel for things like encryption or FEC.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#95

Post by slivym »

sidhu1f wrote: post #85
1024core wrote: post #74

So what can you do with 1.15M logic gates that are in that FPGA? Can you, say, multiply, say 2 256x256 FP32 matrices?

Top of the line Arria-10 FPGAs have about 1500 floating point MACs [1]. Using such a device, Intel claims ~1 TFLOP sustained for GEMM, the standard matrix multiply operation [2]. [1] https://www.altera.com/content/dam/altera-www/global/en_US/p... [2] https://www.altera.com/content/dam/altera-www/global/en_US/p...

I would give a very strong health warning about taking those numbers seriously. What that 2nd reference doesn't make clear is that it is NOT a standard Matrix Multiply Operation, it's an 11 row by 16 column Matrix Multiplication.

This is important because unlike in software where performance scales well. For FPGA you would have to decompose every matrix multiplication into 11x16 style matrix multiplies. They don't mention this overhead in their specs.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#96

Post by slivym »

agumonkey wrote: post #83
vegetablepotpie wrote: post #79

Earlier quoted context omitted.

I can think of two possibilities: 1. Hardware accelerated custom crypto algorithms. 2. Specialized co-processor. You could implement an exotic processing architecture on the FPGA to off-load computations to, like a complex number processor with 52-bit words in a custom floating point format for a specific application.

I don't know how fast the FPGA can reconfigure itself or part of it, but you could also have per process bare metal JIT

It takes in the order of seconds to reconfigure. JIT is not really viable.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#97

Post by slivym »

What I'm really interested to know is how this looks from a power-performance perspective. An Arria 10 can draw 20-40 watts (I'm not sure that 90w is really realistic), and the TDP for the Xeon is 165W. When I saw the discussion about this in the past with people who work at Intel the discussion wasn't 165+90 = 225TDP. It was actually "Oh so you want to use the FPGA, better turn off 6 of those Xeon cores!

That could be a real problem for getting performance out of these systems.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#98

Post by GuB-42 »

vegetablepotpie wrote: post #79
hoodoof wrote: post #73

What's the use case of an integrated FPGA?

I can think of two possibilities: 1. Hardware accelerated custom crypto algorithms. 2. Specialized co-processor. You could implement an exotic processing architecture on the FPGA to off-load computations to, like a complex number processor with 52-bit words in a custom floating point format for a specific application.

Another use case is if you have a large amount of asynchronous I/O and real time constraints.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#99

Post by qubex »

elteto wrote: post #67
bonestamp2 wrote: post #40

Earlier quoted context omitted.

> that bag needs people that write HDL and understand computer architecture to make good use of Over time I suppose they could have some machine learning that automatically configures the FPGA based on which programs you are running and the types of computations they have historically used.

There’s a pretty cool story about using evolutionary algorithms to program an FPGA for a specific task: https://www.damninteresting.com/on-the-origin-of-circuits . Probably not ML in the sense you were talking but very cool nonetheless. In the end the final result was hyperoptimized FPGA code that only ran on a specific board and used a bunch of nonsensical structures that seemed to be doing nothing, yet would stop t…

I remember this, thanks for brining it up,:I had read it years ago and it always haunted me.

The evolved solution involved using only 37 out of the 100 gates available, no clock, and some units were logically disconnected yet disabling them caused the chip to fail at its task, indicating it was relying on EM effects particular to the chip. Truly amazing (and perhaps a bit creepy too).

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#100

Post by qubex »

I remember Faggin (of microprocessor fame) dabbling with the idea of creating an all-FPGA ’hypercomputer’ back in the late 1990s, and even going as far as launching a start-up called Starbridge Systems. Nothing much came of it then, but here’s a WIRED period piece with all the de rigeur gushing optimism of the era.

https://www.wired.com/1999/02/the-super-duper-hypercomputer/

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