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Completely different. myhdl is an alternative to Verilog, but it's still RTL. This tools takes the C code, compiles it to a custom assembler language and embeds the generate assembler code as a ROM in a custom generated RISC processor.
there's no mention of that in first few paragraphs
I had to run the example design to fully understand what it's trying to do.
As an hardware engineer, I'm always skeptical of these homebrewed high level design flows, they usually never seem to translate to good hardware. And it seems to be the case for this one too. I quickly generated some Verilog code from one of the given examples and I was surprised to see flip-flops without reset. Also, not all registers are even being reset'ed at all. I have some serious doubts about the quality of th…
However, if it targets FPGA, and not ASICs, maybe the reset omission is on purpose. FPGA guarantees initialization on load and the some registers may not need to be cleared after usage. On the other hand, a reset signal consumes precious routing resources spanning large areas.
But I surely would triple-check this, even for FPGA use. I expect to actually do so in a few weeks.
EDIT: Ok, this comment sit far too long in the edit box before posting. Now I see the huge discussion in this thread. I'll keep this comment anyway.
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This. GP's comment is way old school. For most FFs in your designs, reset is unnecessary. Ken Chapman at Xilinx wrote some wonderful whitepapers about that; look them up. Join us in enlightenment, brother.
It's not old school, it's standard practice in the ASIC design industry. You mentioned those papers but you didn't link them, so I will have to guess that this is the one in order to address your comment: - https://www.xilinx.com/support/documentation/white_papers/wp... I guess the keyword here is "FPGA design". The author of the paper argues that the FPGA already offers an abstraction layer that allows the designer…
Very interesting. Please take note that this is not your usual transpiler such as MyHDL or Migen: "Behind the scenes, Chips uses some novel techniques to generate compact and efficient logic - a hybrid of software and hardware. Not only does the compiler translate the C code into CPU instructions, it also generates a customised pipelined RISC CPU on the fly. The CPU provides the optimal instruction set for any partic…
Very interesting. Please take note that this is not your usual transpiler such as MyHDL or Migen: "Behind the scenes, Chips uses some novel techniques to generate compact and efficient logic - a hybrid of software and hardware. Not only does the compiler translate the C code into CPU instructions, it also generates a customised pipelined RISC CPU on the fly. The CPU provides the optimal instruction set for any partic…
I wonder what it would do if you compiled a small Lisp or Scheme interpreter that included eval with it.
However, I would not raise my expectations that much.
Earlier quoted context omitted.
I wonder what it would do if you compiled a small Lisp or Scheme interpreter that included eval with it.
I'm not sure if I have the software skills for that (my compilers course is still pending in Coursera), but will try to do it! However, I would not raise my expectations that much.
Not sure how FPGAs do their thing but a swapping out fgets() with something else and setting up the garbage collector to use one block of memory would probably be necessary I'd imagine.
Earlier quoted context omitted.
I'm not sure if I have the software skills for that (my compilers course is still pending in Coursera), but will try to do it! However, I would not raise my expectations that much.
You could try one of the minischeme implementations floating around github without too much fuss. Not sure how FPGAs do their thing but a swapping out fgets() with something else and setting up the garbage collector to use one block of memory would probably be necessary I'd imagine.
But I don't expect not very interesting to happen. The " CPU optimization" will not result on a Lisp Machine. It will probably just compile the interpreter as usual and prune unnecessary instructions.