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TSMC Kicks Off Volume Production of 7nm Chips

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Re: TSMC Kicks Off Volume Production of 7nm Chips

#71
post #65

Earlier quoted context omitted.

I've always assumed that "XX nm" doesn't represent the geometry of any particular feature of the end product, but something related to the wavelength of the radiation used for the imaging process. Maybe it corresponds to the principle emission line of the light source (synchrotron?) In spectral terms, 7 nm is near the border between hard UV radiation and soft X-rays.

This is not correct at all. Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep Ultraviolet Lithography" (DUV(L)). The industry is pushing towards replacing DUV (which has been pushed to its extremes) with "Extreme Ultraviolet Lithography" (EUV(L)), which uses a 13.5 nm light source (just watch https://www.youtube.com/watch?v=5yTARacBxHI -…

So, what does determine the "marketing" nomenclature for a given process node, if not a specific feature size or wavelength?

I find it impossible to believe that some obscure semiconductor industry people get together in a hidden smoke-and-particulate-matter-free room, come up with a completely-random number, and name their process after it.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#72
post #29
post #20

Earlier quoted context omitted.

Well that's annoying. How is anyone supposed to judge anything if they just make numbers up?

I think bits of SRAM per unit of area is a benchmark that some people use, as it corresponds to something that's meaningful and measurable.

The problem is even that is flawed as things are going three dimensional.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#73
post #57

Earlier quoted context omitted.

I think you linked to a flip chip---you would expect a mirror finish from the bulk silicon side.

Ah yes you're right of course. Has there been anything in the past few years made on modern processes with the die actually visible? Desktop/laptop CPUs and GPUs have all been flip chip for at least the past decade, mobile SoCs are package on package, most other stuff is encased in plastic.

der8auer did flip the Zen dies in the Threadripper over and ground them down to look what's inside.

The video gives a good impression of the dimensions of the die and the structures inside.

https://youtu.be/N-uKQ6RfUdk

Re: TSMC Kicks Off Volume Production of 7nm Chips

#74

Fun stuff. I've got a key chain with an 80186 die, and a couple of the binders from Microprocessor Forum when they had dies on the cover. The features on those chips are "huge" compared to these things. I suspect a die using one of these processes that was big enough (say 100 sq mm) would just look like a mirror with chromatic interference lines running across it. This announcement also bookends nicely with the first…

when we went above ~3 metal layers upper layers started to be used power and ground planes - that tends to mean that you can't really see much any more

Re: TSMC Kicks Off Volume Production of 7nm Chips

#75
post #65

Earlier quoted context omitted.

This is not correct at all. Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep Ultraviolet Lithography" (DUV(L)). The industry is pushing towards replacing DUV (which has been pushed to its extremes) with "Extreme Ultraviolet Lithography" (EUV(L)), which uses a 13.5 nm light source (just watch https://www.youtube.com/watch?v=5yTARacBxHI -…

So, what does determine the "marketing" nomenclature for a given process node, if not a specific feature size or wavelength? I find it impossible to believe that some obscure semiconductor industry people get together in a hidden smoke-and-particulate-matter-free room, come up with a completely-random number, and name their process after it.

It's worse than that... there's not jist an industry group (ITRS), there's also the foundries making it up themselves. They're buying similar equipment and selling similar transistor densities (except for Intel which has finer geometries and higher densities for a given node), but few are directly compatible on density, clock-rate, or power consumption after 28nm.

https://en.m.wikipedia.org/wiki/International_Technology_Roa...

Scalling really started falling apart in the late 90s around .25u, and then (incidentally) about the time CPU MHZ stopped scaling... by 65nm both gate and transistor length got wonky. Then after 28nm they moved to fin-FETs and multi-patterning making comparisons even more difficult.

https://semiengineering.com/a-node-by-any-other-name/

Re: TSMC Kicks Off Volume Production of 7nm Chips

#76
post #74

Fun stuff. I've got a key chain with an 80186 die, and a couple of the binders from Microprocessor Forum when they had dies on the cover. The features on those chips are "huge" compared to these things. I suspect a die using one of these processes that was big enough (say 100 sq mm) would just look like a mirror with chromatic interference lines running across it. This announcement also bookends nicely with the first…

when we went above ~3 metal layers upper layers started to be used power and ground planes - that tends to mean that you can't really see much any more

I hadn't thought of that. It will make the chip decapping people sad as well because you really need xrays to see through the metal layers.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#77

So one of the most important questions when producing >10nm process is yield . In the article I can't really find yield numbers, and the only thing they mention is the SRAM chips getting "consistent double digits" -- so pessimistically consistently 10% yield. That's not "good" yield. Also, IIRC SRAMs are just about the simplest blocks you can make, which means they're the simplest lithography wise. Simple blocks to m…

I think you mean <10 nm?

Re: TSMC Kicks Off Volume Production of 7nm Chips

#78
post #65

Earlier quoted context omitted.

This is not correct at all. Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep Ultraviolet Lithography" (DUV(L)). The industry is pushing towards replacing DUV (which has been pushed to its extremes) with "Extreme Ultraviolet Lithography" (EUV(L)), which uses a 13.5 nm light source (just watch https://www.youtube.com/watch?v=5yTARacBxHI -…

So, what does determine the "marketing" nomenclature for a given process node, if not a specific feature size or wavelength? I find it impossible to believe that some obscure semiconductor industry people get together in a hidden smoke-and-particulate-matter-free room, come up with a completely-random number, and name their process after it.

It used to be a specific feature size: the length of the gate. But, even as the wheels came off of that pretty quickly, the convention stayed pretty simple and familiar: each process node halves the size of the one before it - you can print double the number of transistors at the smaller process node. To make the math work out, that means each process node "name" is sqrt(1/2) ~= 0.7x smaller than the last, which gives you the easy-to-follow node names from 3um to about 3nm (when people tend to switch to ångströms or picometers since it moves the decimal kindly).

Even as things got sticky due to advancements in transistor construction meaning that old metrics like gate length were obsolete, we were still roughly following the trend laid out ahead of us for decades. A new process would double your density, letting you roughly cut the size of your old chip in half.

...Until a few fab companies just up and decided "You know what, fuck it, we can't actually catch up to Intel, but if what if we just... say that we did?" (...and I wish I was kidding. Take a look: https://m.eet.com/images/eetimes/2013/10/1319679/20-Value.jp... vs https://m.eet.com/images/eetimes/2013/10/1319679/16-Value.jp...).

So pretty quickly, TSMC decided that they'd just advance the node table, despite not actually increasing the density by double as you'd expect. "Next generation" 20nm processes became "16nm" and "14nm" on marketing docs, despite the process capabilities not changing that much (or even at all in some cases), with the only thing close to a justification given is that "FinFETs are different. They perform better than planar FETs so we should be able to give them a new node name." GloFo and Samsung quickly took the bit and followed their lead as they began FinFET manufacturing.

And apparently since nobody blinked an eye or set off alarm bells about these fabs basically lying about their capabilities, they got away with it and are now continuing the trend downwards. "10nm" processes from TSMC, Samsung and GloFo measure up to Intel's 14nm, and now "7nm" processes measure up to Intel's 10nm. It's actually pretty surprising Intel hasn't thrown up its hands and joined them on the fun, or even come up with their own marketing spin on it yet. "Intel's new 7nm-xtreme manufacturing process (actually it's just 10nm+)" or whatever.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#79
post #65

Earlier quoted context omitted.

I've always assumed that "XX nm" doesn't represent the geometry of any particular feature of the end product, but something related to the wavelength of the radiation used for the imaging process. Maybe it corresponds to the principle emission line of the light source (synchrotron?) In spectral terms, 7 nm is near the border between hard UV radiation and soft X-rays.

This is not correct at all. Most chips made today are created with multipatterning processes using 193nm lasers and optical masks, known in the field as "Deep Ultraviolet Lithography" (DUV(L)). The industry is pushing towards replacing DUV (which has been pushed to its extremes) with "Extreme Ultraviolet Lithography" (EUV(L)), which uses a 13.5 nm light source (just watch https://www.youtube.com/watch?v=5yTARacBxHI -…

>- it's both fascinating and terrifying the trouble that EUV brings

It is only peanuts in comparison to what is to come. The "nuclear option" on the table is to build a whole fab around a freaking synchrotron light source.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#80
post #44
post #14

Earlier quoted context omitted.

There isn't any feature of the transistors taht are 7nm wide, the smallest feature IIRC is the interconnect, which is about 30n-40nm. "7nm" is marketing wankery. https://en.wikichip.org/wiki/7_nm_lithography_process

If you look at the SRAM bit cells, they halved in area from 28nm to 14nm, and halved again from 14nm to 7nm. This is likely due to metal interconnects or other features only halving in spacing going from 28nm process to 7nm. So the scaling almost appears to apply to only one dimension (full linear scaling of two dimensions would have quartered the cell area at each step resulting in a 16-fold total reduction). But it…

Wait for 3d sram
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