Live data from Hacker News

TSMC Kicks Off Volume Production of 7nm Chips

anandtech.com

51–60 of 111 posts

Re: TSMC Kicks Off Volume Production of 7nm Chips

#51
post #2

It's just stunning how they have been able to achieve 7nm features. With a 193nm wavelength laser no less.

1. Not really 7nm, only the fin width is ~7nm, metals, etc are more like 54nm.

2. Immersion lithography (water as refractive index) + multiple patterning + computational lithography.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#52
post #28

Earlier quoted context omitted.

The gate pitch is 54mm for TSMC and 56nm for Global Foundries @ 7nm.

> 54mm Typo for nm, presumably :-).

The funny thing about 54mm is that this is pretty close to the original gate pitch, back when we had to use vacuum tubes or relays.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#53
So one of the most important questions when producing >10nm process is yield. In the article I can't really find yield numbers, and the only thing they mention is the SRAM chips getting "consistent double digits" -- so pessimistically consistently 10% yield. That's not "good" yield.

Also, IIRC SRAMs are just about the simplest blocks you can make, which means they're the simplest lithography wise. Simple blocks to make, so they're usually good candidates for exploration of new process...

7nm is hard (I've said in a previous post, but you're just fighting physics at that point, nevermind all the issues you start facing with crosstalk/etc), color me skeptical that they've really nailed down a "volume" process for doing it just yet.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#54
post #18

I have a question - why does the fab machine lithographic printing etch out a half a chip on the edge of the wafer like in the article picture. I presume the wafers are a standard 300mm size, so is it just because the designers were too lazy to remove the half chips on the edges from their mask template designs ?

Aha I had a question too why wafers are round. The answer is Crystals form in a cylinder then sliced. https://en.wikipedia.org/wiki/Wafer_(electronics)#Formation . Sorry it doesn't answer your question but helped me. :)

You could slice a cylinder the other way. That would give you rectangles, with the short dimension varying. I'm not so sure you'd save any space, but recycling the unused portion might be more reasonable to do.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#55

I have a question - why does the fab machine lithographic printing etch out a half a chip on the edge of the wafer like in the article picture. I presume the wafers are a standard 300mm size, so is it just because the designers were too lazy to remove the half chips on the edges from their mask template designs ?

If your chips aren't very large, you can fit multiple copies in the reticle. E.g., if the litho machine has a 40mm by 50mm reticle, and you're making a 10mm by 10mm die, you can expose 20 dice at a time. It's usually worth it to go out to the edges even if you only get a few complete chips from the exposure. I can't find a wafer picture for Nvidia's GV100, but presumably a giant chip like that uses the whole reticle, so I don't expect to see partial chips on its wafer.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#57
post #35

Earlier quoted context omitted.

ICs have just looked like mirrors for a while now. See this shot of a 14nm Vega die on the left and 28nm Fury die on the right: https://www.techpowerup.com/reviews/AMD/Radeon_RX_Vega_Previ...

I think you linked to a flip chip---you would expect a mirror finish from the bulk silicon side.

Ah yes you're right of course. Has there been anything in the past few years made on modern processes with the die actually visible? Desktop/laptop CPUs and GPUs have all been flip chip for at least the past decade, mobile SoCs are package on package, most other stuff is encased in plastic.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#58
post #54
post #18

Earlier quoted context omitted.

Aha I had a question too why wafers are round. The answer is Crystals form in a cylinder then sliced. https://en.wikipedia.org/wiki/Wafer_(electronics)#Formation . Sorry it doesn't answer your question but helped me. :)

You could slice a cylinder the other way. That would give you rectangles, with the short dimension varying. I'm not so sure you'd save any space, but recycling the unused portion might be more reasonable to do.

The manufacturing process for semiconductors uses a standardized wafer size (in a given fab) so everything can be automated and simplified as far as possible. Having even something like just two wafer sizes makes a lot of the tooling/storage/transfer more complicated and expensive, so it's best to stick to one size and shape.

In order to have uniform rectangular slices of the silicon crystal, you'd have to slice off horizontal cylinder segments. And that would defeat the purpose because if you just used circular wafers you'd have been able to get a couple dies out of that area.

Re: TSMC Kicks Off Volume Production of 7nm Chips

#59
post #2

It's just stunning how they have been able to achieve 7nm features. With a 193nm wavelength laser no less.

It’s not 7nm in any feature size it’s seceral times that. It’s achievable usually with multiple patterning and submersion 193nm wavelength in vacuum which goes to about 145 in water and they likely are using something other than water and you also have temperature which affects the refractive index.

[deleted]

Re: TSMC Kicks Off Volume Production of 7nm Chips

#60

So one of the most important questions when producing >10nm process is yield . In the article I can't really find yield numbers, and the only thing they mention is the SRAM chips getting "consistent double digits" -- so pessimistically consistently 10% yield. That's not "good" yield. Also, IIRC SRAMs are just about the simplest blocks you can make, which means they're the simplest lithography wise. Simple blocks to m…

Yields will suffer with current DUV process which must be multiple, multiple patterning. The mentioned switch to EUV reduces multiple patterning and should improve yield. But EUV has had its own challenges.
Post reply on HN