Itsy-Chipsy: Make your own $100 ASIC
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Itsy-Chipsy: Make your own $100 ASIC
1–8 of 8 posts
Re: Itsy-Chipsy: Make your own $100 ASIC
#2Using a 180 nm process, this isn't going to outperform an FPGA at 14 nm either on clock rate or power. And the iteration time will be several weeks instead of minutes. So I'm curious what use cases this will have -- maybe something that doesn't fit into the FPGA mold like asynchronous logic?
Re: Itsy-Chipsy: Make your own $100 ASIC
#3Using a 180 nm process, this isn't going to outperform an FPGA at 14 nm either on clock rate or power. And the iteration time will be several weeks instead of minutes. So I'm curious what use cases this will have -- maybe something that doesn't fit into the FPGA mold like asynchronous logic?
Depends on clock rate. This is not for building a microprocessor.
Static power on 180 nm circuit should be negligible, which won't be the case on a 14 nm FPGA.
Re: Itsy-Chipsy: Make your own $100 ASIC
#4Using a 180 nm process, this isn't going to outperform an FPGA at 14 nm either on clock rate or power. And the iteration time will be several weeks instead of minutes. So I'm curious what use cases this will have -- maybe something that doesn't fit into the FPGA mold like asynchronous logic?
Guessing following cases: 1) Education 2) Synthesized analog functions: PLL, ADC, DAC, Filters, etc. 3) Do your own standard cells using a new kind of logic 4) Proof-of-concept for analog circuitry
Re: Itsy-Chipsy: Make your own $100 ASIC
#5Since all circuitry from different projects will be inside a single chip, and all circuits are accessible through the same platform, how do you plan to offer digital privilege access/circuitry protrction to each chip? I mean, random data can be push to jtag (for example) and get results for every circuit embedded inside this chip.
Re: Itsy-Chipsy: Make your own $100 ASIC
#6Since all circuitry from different projects will be inside a single chip, and all circuits are accessible through the same platform, how do you plan to offer digital privilege access/circuitry protrction to each chip? I mean, random data can be push to jtag (for example) and get results for every circuit embedded inside this chip.
We've been thinking on this. It is definitely a though issue but it is not different from the opportunity of decapping a commercial chip and try to get IP from there. There a three options we have been thinking: 1. Obfuscated register mapping with a synced TRNG, 2. A light cipher. 3. Physical and structural logic obfuscation. The area overhead is an issue and we are trying to gather some results from an internal research going on to see feasibility.
Re: Itsy-Chipsy: Make your own $100 ASIC
#7Using a 180 nm process, this isn't going to outperform an FPGA at 14 nm either on clock rate or power. And the iteration time will be several weeks instead of minutes. So I'm curious what use cases this will have -- maybe something that doesn't fit into the FPGA mold like asynchronous logic?
Prototyping of novel circuits (e.g. async), 3D integration, education, etc.
It's a really useful thing to be honest.
Re: Itsy-Chipsy: Make your own $100 ASIC
#8Who cares about performance as long as it works?
Pretty sure you're all missing the point.
The point is that a kid working fast food during the day and OpenChip/OpenCores enthusiast at night could build whatever they're thinking of over summer vacation.
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