Implementing FizzBuzz on an FPGA • Hacker News Board

Re: Implementing FizzBuzz on an FPGA

#51

Post by FPGAhacker » Wed, Mar 14, 2018, 3:00 AM UTC

pjmlp wrote: post #27

vvanders wrote: post #10

> While this may look like code in a normal programming language, it operates entirely differently. So happy to see this called out up-front. One of the hardest things with FPGAs as a developer is understanding that you're reconfiguring hardware instead of a series of serial asm/opcodes. They look superficially the same but have very different requirements and constraints under the hood.

It depends very much where we as developers come from. My CS degree had quite a few sections of electronic lectures. In fact, one way I always looked at function composition in FP languages was to think of them as digital circuit modules.

I think there are many parallels between functional programs and electronic circuits. Many design concepts and disciplines of software can be applied to digital design. The idea of actors and message passing very naturally applies itself to digital design.

Combinational logic is functional as long as you keep feedback loops out of it. For a given input, you will always get a particular output. Eventually. Time is a factor.

Unlike software, this bit of functional logic is "on" or "active" all the time though. At any given moment, there is something at the input and something at the output. It's like a pair of sunglasses. They are always sunglassing, light is going through them and being filtered, whether you are using them or not.

Adding state is necessary for anything but the most trivial designs. And like software, state makes things more complicated. We call the logic that implements state "sequential" logic. By that token, instead of Combinational, we could call it Concurrent logic.

Actors could be a logical grouping of combinational and sequential logic. Pure functions and state. With ports for messaging.

Re: Implementing FizzBuzz on an FPGA

#52

Post by 8note » Wed, Mar 14, 2018, 3:12 AM UTC

cesarb wrote: post #15

Would it have been better to use a ring counter instead of an adder for the modulo 3, modulo 5, and state counters?

significantly more efficient and fpga-like

Re: Implementing FizzBuzz on an FPGA

#53

Post by smalley » Wed, Mar 14, 2018, 3:39 AM UTC

pitaj wrote: post #45

eebynight wrote: post #7

Earlier quoted context omitted.

Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.

I know Intel uses Verilog.

The majority of Intel's newly developed HDL is systemVerilog on the design and verification side, but honestly there is still a mix of everything going on there.

Some chip designs make use of purchased IP which is at times VHDL. Heck some unit owners and architects even experimented with HLS (High Level Synthesis) using SystemC for part of the graphics hardware and a few units still have state machines which automatically translate from a DSL or word macros.

I do think both of the trends people are identifying hold true though. US is more verilog than not, Europe I see more VHDL than verilog. US exceptions are typically FPGA developers and defense contractors (but definitely not universally).

In my opinion I find systemVerilog to be much easier to design in with less verbose syntax, better tooling and some nice constructs that make realizing design intent easier. systemVerilog always blows away VHDL in testbench design and general verification environment support. I would never wish designing an elaborate testbench in VHDL on an engineering team. VHDL does have some advantages if you have requirements to do a lot of formal property verification though.

Re: Implementing FizzBuzz on an FPGA

#54

Post by Crisco » Wed, Mar 14, 2018, 5:07 AM UTC

gh02t wrote: post #14

leggomylibro wrote: post #8

Earlier quoted context omitted.

I got a couple of ICESticks I've been meaning to play with a little while ago, they're only $25 MSRP and have a 'USB stick' form factor. But it's hard to find and get started with a good open source toolchain. I have heard good things about IceStorm, but haven't gotten around to setting it up. It's great and inspiring to see people successfully stepping through these sorts of starter projects and documenting them, th…

> But it's hard to find and get started with a good open source toolchain That's because there aren't any. The one you have happens to be the exception - it's the only FPGA line with an open source toolchain AFAIK. FPGAs are the realm of large, heavily proprietary build environments.

I was complaining about that the other day. I'm a pretty big fan and proponent of the Libre software movement and have recently decided I want to help with an open hardware movement because it is almost impossible to do any serious work with FPGAs using only FOSS. Does anyone know of any good places to start and help?

Re: Implementing FizzBuzz on an FPGA

#55

Post by _pmf_ » Wed, Mar 14, 2018, 5:53 AM UTC

TomVDB wrote: post #18

For those looking for cheap FPGA boards, I highly recommend looking for something that is based on the Lattice ICE40. The cheapest board you can find is probably the $9 Upduino, though trickier to get going. (Complete lack of documentation.) But there are tons of hobby boards in existence. The best part is Project IceStorm, a fully open source tool flow, from synthesis to bitstream. While not the best in terms of opt…

PSoCs are nice, too. They're not full blown FPGAs, but you can experiment with Verilog pretty easily.

Re: Implementing FizzBuzz on an FPGA

#56

Post by [deleted] » Wed, Mar 14, 2018, 7:53 AM UTC

vvanders wrote: post #41

pjmlp wrote: post #38

Earlier quoted context omitted.

And you missed mine, as I mentioned that we had electronic lectures. I am not talking out of thin air and wild guesses how things should be, rather about my personal experience how we learned digital circuit design and how later, already with that skill, we applied the ideas to FP. That was the goal of my initial comment, Hardware Design Ideas -> Help understating FP function combinations as if they were ICs, not how…

Didn't miss it, just don't think they're equivalent. I appreciate functional programming and block diagrams/black box design are great tools for that space. However they don't capture the nuance of circuit design that goes into FPGA development. You can't capture pipeline depth, SRAM usage, thermal envelope/clock gating that have significant real world impacts on your design.

[deleted]

Re: Implementing FizzBuzz on an FPGA

#57

Post by sguav » Wed, Mar 14, 2018, 9:19 AM UTC

I am pleasantly surprised by this reading!

I have been trained as an EE to consider FPGA design in the hardware skills domain, and indeed I would say that this writeup ignores the less friendly parts of FPGA development (timing closure, clock domain crossing and more...). Nevertheless, I think it is a good introduction for software developers to start thinking like "hardware description". Good work!

Re: Implementing FizzBuzz on an FPGA

#58

Post by imtringued » Wed, Mar 14, 2018, 11:09 AM UTC

mrguyorama wrote: post #6

The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy

But as soon as you want a board with high bandwidth IO a single board costs more than a high end laptop or desktop or low end workstation.

Re: Implementing FizzBuzz on an FPGA

#59

Post by mrguyorama » Wed, Mar 14, 2018, 3:28 PM UTC

aldanor wrote: post #42

mrguyorama wrote: post #6

The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy

... or how expensive the ‘real’ boards are, e.g. $7K for a Xilinx US+.

How does that compare to the unit price of making a few comparable prototypes in raw silicon?

Re: Implementing FizzBuzz on an FPGA

#60

Post by gh02t » Wed, Mar 14, 2018, 6:48 PM UTC

Crisco wrote: post #54

gh02t wrote: post #14

Earlier quoted context omitted.

> But it's hard to find and get started with a good open source toolchain That's because there aren't any. The one you have happens to be the exception - it's the only FPGA line with an open source toolchain AFAIK. FPGAs are the realm of large, heavily proprietary build environments.

I was complaining about that the other day. I'm a pretty big fan and proponent of the Libre software movement and have recently decided I want to help with an open hardware movement because it is almost impossible to do any serious work with FPGAs using only FOSS. Does anyone know of any good places to start and help?

The Lattice boards mentioned above are a good start. Really they're your only choice since they're the only open source toolchain, but the iCEStick is a pretty good place to start. It's a decent FPGA in a USB stick form factor and it's self contained so you don't need an external programmer. At $25 it won't break the bank.

If you meant more how to get involved with the community effort, I'd start with Clifford Wolf's page (http://www.clifford.at/icestorm/ ). He's the main guy behind the efforts with the iCE40 toolchain and his page links to some other efforts to reverse engineer Xilinx and Altera chips. There's a lot of interest in more open FPGAs, but I think there's a lack of skilled people so you'd likely be welcome.