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Intel has released new CPU microcode for download

downloadcenter.intel.com

31–40 of 112 posts

Re: Intel has released new CPU microcode for download

#32

Earlier quoted context omitted.

What about those of us still on 10.11? That one is horrible already but the horror stories I see on a daily base from colleagues with 10.12/10.13, thanks but no thanks... I'm not a free QA engineer for Apple.

You (and colleagues) must have a strange workload. Despite my misgivings about an in-place file system change, the switch to 10.13 was pretty much painless. I use software from the latest Apple stuff, to aging programs from Adobe and other third parties, to GNU Emacs, to scripts written decades ago, so it doesn't seem like general breakage.

> You (and colleagues) must have a strange workload.

Sometimes it's something as easy as installing the printer driver for a C1028i printer. On 10.13, it's stuck on "Configuring printer" forever. The printer driver is the currentmost available from the vendor, and the OS fully patched.

Or something as grave as the famous empty password root backdoor. This alone is sufficient for me to not upgrade as long as possible - when something like this manages it into production, what else got missed?

Re: Intel has released new CPU microcode for download

#33
post #15

FWIW, microcode is now included the patch that VMware released today. Gonna go test it out now... PSA: VMs have to be cold booted after patching and set to HW v11+ for PCID support EDIT: Just fired up my first Windows VM after patching ESXI and I'm now showing all green using the PowerShell script. Here's the link that I'm referring to: https://www.vmware.com/us/security/advisories/VMSA-2018-0004...

Yikes. So they refuse to vMotion to a host that's on the new microcode? I'm not even clear on how that would be supported -- it should Just Work if the host is in the cluster. Are hosts unable to rejoin a cluster after rebootign with this new microcode because they're effectively part of a different processor compatibility now? Does EVC affect how this impacts the ability to vMotion?

The problem (requiring the cold reboot of the VM) is that they masked the PCID bit off in the CPUID, so the VM thinks it is running on a CPU that doesn't support PCID. Obviously they've stopped doing this with the new update, but you have to cold reboot (not warm) for the newly enabled feature to be visible.

Presumably they did this to make it possible to hot migrate VMs between old hosts that don't support PCID, and new ones that do. Which, with hindsight, was not a good tradeoff.

Re: Intel has released new CPU microcode for download

#34
post #33
post #15

Earlier quoted context omitted.

Yikes. So they refuse to vMotion to a host that's on the new microcode? I'm not even clear on how that would be supported -- it should Just Work if the host is in the cluster. Are hosts unable to rejoin a cluster after rebootign with this new microcode because they're effectively part of a different processor compatibility now? Does EVC affect how this impacts the ability to vMotion?

The problem (requiring the cold reboot of the VM) is that they masked the PCID bit off in the CPUID, so the VM thinks it is running on a CPU that doesn't support PCID. Obviously they've stopped doing this with the new update, but you have to cold reboot (not warm) for the newly enabled feature to be visible. Presumably they did this to make it possible to hot migrate VMs between old hosts that don't support PCID, and…

Given that Linux (and most other VM guest OSes of note) support CPU hotplug, shouldn't vMotion have just given the VM a new, second CPU with PCID, and then removed the first one?

Re: Intel has released new CPU microcode for download

#36
post #35
post #28

Does AMD also need some microcode update for this?

https://www.amd.com/en/corporate/speculative-execution They claim no, due to microarchitectural differences in their branch predictor behavior. This is variant 2 we're talking about here.

So I guess just kernel updates for Spectre are needed.

Re: Intel has released new CPU microcode for download

#37
post #36
post #35

Earlier quoted context omitted.

https://www.amd.com/en/corporate/speculative-execution They claim no, due to microarchitectural differences in their branch predictor behavior. This is variant 2 we're talking about here.

So I guess just kernel updates for Spectre are needed.

Supposedly just for 1 of the 2 main variants of Spectre.

Though there are many likely more timing channels that could be reasonably called Spectre variants that have not yet been fully explored...

Re: Intel has released new CPU microcode for download

#39
post #34
post #33

Earlier quoted context omitted.

The problem (requiring the cold reboot of the VM) is that they masked the PCID bit off in the CPUID, so the VM thinks it is running on a CPU that doesn't support PCID. Obviously they've stopped doing this with the new update, but you have to cold reboot (not warm) for the newly enabled feature to be visible. Presumably they did this to make it possible to hot migrate VMs between old hosts that don't support PCID, and…

Given that Linux (and most other VM guest OSes of note) support CPU hotplug, shouldn't vMotion have just given the VM a new, second CPU with PCID, and then removed the first one?

Given the history of CPU hot plug, it has always been generally assumed that all the CPUs in an SMP are identical (hence the S in SMP). I'm not aware of any OS that supports differing feature sets, and if one exists, it almost certainly goes with the least common denominator feature set.

Re: Intel has released new CPU microcode for download

#40

Literally tells us nothing about what's in it. Not even a changelog. Not even a sentence hinting as to what might be in it. Incredible.

> Literally tells us nothing about what's in it. Not even a changelog. Not even a sentence hinting as to what might be in it. Incredible.

They do have ./releasenote:

  Intel Processor Microcode Package for Linux 20180108 Release
  -- Updates upon 20171117 release --
  IVT C0            (06-3e-04:ed) 428->42a
  SKL-U/Y D0        (06-4e-03:c0) ba->c2
  BDW-U/Y E/F       (06-3d-04:c0) 25->28
  HSW-ULT Cx/Dx     (06-45-01:72) 20->21
  Crystalwell Cx    (06-46-01:32) 17->18
  BDW-H E/G         (06-47-01:22) 17->1b
  HSX-EX E0         (06-3f-04:80) 0f->10
  SKL-H/S R0        (06-5e-03:36) ba->c2
  HSW Cx/Dx         (06-3c-03:32) 22->23
  HSX C0            (06-3f-02:6f) 3a->3b
  BDX-DE V0/V1      (06-56-02:10) 0f->14
  BDX-DE V2         (06-56-03:10) 700000d->7000011
  KBL-U/Y H0        (06-8e-09:c0) 62->80
  KBL Y0 / CFL D0   (06-8e-0a:c0) 70->80
  KBL-H/S B0        (06-9e-09:2a) 5e->80
  CFL U0            (06-9e-0a:22) 70->80
  CFL B0            (06-9e-0b:02) 72->80
  SKX H0            (06-55-04:b7) 2000035->200003c
  GLK B0            (06-7a-01:01) 1e->22
  
But I'm not sure how to interpret it... BDW is probably Broadwell and HSW is probably Haswell etc., IVT is... interrupt vector table? and I'm not sure what the other characters are.
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