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Meltdown Proof-of-Concept

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61–70 of 187 posts

Re: Meltdown Proof-of-Concept

#61

Earlier quoted context omitted.

If you don't know the difference between the existence of an earthbound asteroid and the existence of people who write computer viruses, I don't know what to tell you.

What's the name for this logical fallacy? You see this shit all the time.

"Bullshitting"?

Re: Meltdown Proof-of-Concept

#62

Earlier quoted context omitted.

If you don't know the difference between the existence of an earthbound asteroid and the existence of people who write computer viruses, I don't know what to tell you.

What's the name for this logical fallacy? You see this shit all the time.

I like false equivocation.

Re: Meltdown Proof-of-Concept

#63
post #43
post #41

MacOS is yet to have a patch for 10.12.6 (Sierra) to resolve this.

Did you get the PoC built on macOS? I can't get it built on El Capitan.

Not any of the PoC. There are repositories around the internet building and working successfully though. E.g. Spectre exploit example https://github.com/ixtal23/spectreScope

Re: Meltdown Proof-of-Concept

#64
I'm curious if someone can point me to any source that discusses how the next generation of CPUs that Intel, AMD, ARM might be working on is actually going to address this & the Spectre issue architecturally.. It's great that we have a potentially performance killing fix but the real "fix" or rather, solution, is to alter the architecture. Since I'm not an EE/CE dude... is anyone aware of where such discussions on the WWW might be taking place?

by the way, that PoC was intense. Makes you wonder if the NSA knew about it all along :)

Re: Meltdown Proof-of-Concept

#65
post #63
post #43

Earlier quoted context omitted.

Did you get the PoC built on macOS? I can't get it built on El Capitan.

Not any of the PoC. There are repositories around the internet building and working successfully though. E.g. Spectre exploit example https://github.com/ixtal23/spectreScope

FWIW, that PoC (reading user memory only) still works on 10.13.2 even after the patch is applied.

Re: Meltdown Proof-of-Concept

#66
post #60

Earlier quoted context omitted.

Well, since some of the BSD folks publicly stated that they’d ignore any embargo, that seems like a pretty predictable consequence. And in this case I understand that it took a while to develop workable mitigations. Immediate disclosure might have caused great harm.

Tarring all of the BSDs with the same brush is wrong, both in general and here specifically. There's also the matter of both Matthew Dillon and Theo de Raadt discussing this topic months or even years before Google Project Zero made its discovery. * https://news.ycombinator.com/item?id=16086047 * https://news.ycombinator.com/item?id=16074531 * https://news.ycombinator.com/item?id=16075744 Moreover, the OpenBSD people…

The bugs Theo was talking about were unrelated to these ones.

Re: Meltdown Proof-of-Concept

#67

These two bugs (Meltdown and Spectr) are really very speculative things. It is like when human beings became aware of astroid orbits they thought that earth is in danger of being hit by one. Now that is indeed a theoritical possibility but what are the chances? These two bugs have been existent for 20 years and there is no known exploits of them. In the GitHub demos also they mention that the demos will work only if…

This is literally a PoC. It's too late for the standard "I can't imagine how to exploit this so surely it cannot be done" fallacy. You are looking at an example of how to do it.

From the README - “For this demo, you either need the direct physical map offset (e.g. from demo #2) or you have to disable KASLR by specifying nokaslr in your kernel command line." - what do you think are the percentages of systems that match these conditions?

Re: Meltdown Proof-of-Concept

#68

I'm curious if someone can point me to any source that discusses how the next generation of CPUs that Intel, AMD, ARM might be working on is actually going to address this & the Spectre issue architecturally.. It's great that we have a potentially performance killing fix but the real "fix" or rather, solution, is to alter the architecture. Since I'm not an EE/CE dude... is anyone aware of where such discussions on th…

To my understanding, the memory subsystem is fetching a byte in parallel with access permission checks. If the byte is discarded due to mis-speculation, then the result of the permission check is ignored, but the cache is still in an updated state.

I believe one solution would be to put permission checks before the memory access, which would add serialized latency to all memory access. Another would be to have the speculative execution system flush cache lines that were loaded but ultimately ignored, which would be complex but probably not be as much of a speed hit.

(edit: yeah, a simple "flush" is insufficient, it would have to be closer to an isolated transaction with rollback of the access's effects on the cache system.)

Re: Meltdown Proof-of-Concept

#69

I'm curious if someone can point me to any source that discusses how the next generation of CPUs that Intel, AMD, ARM might be working on is actually going to address this & the Spectre issue architecturally.. It's great that we have a potentially performance killing fix but the real "fix" or rather, solution, is to alter the architecture. Since I'm not an EE/CE dude... is anyone aware of where such discussions on th…

To my understanding, the memory subsystem is fetching a byte in parallel with access permission checks. If the byte is discarded due to mis-speculation, then the result of the permission check is ignored, but the cache is still in an updated state. I believe one solution would be to put permission checks before the memory access, which would add serialized latency to all memory access. Another would be to have the sp…

the first approach sounds kind of expensive to be done at the cpu level. I like your second one better. thank you!

Re: Meltdown Proof-of-Concept

#70

Earlier quoted context omitted.

To my understanding, the memory subsystem is fetching a byte in parallel with access permission checks. If the byte is discarded due to mis-speculation, then the result of the permission check is ignored, but the cache is still in an updated state. I believe one solution would be to put permission checks before the memory access, which would add serialized latency to all memory access. Another would be to have the sp…

the first approach sounds kind of expensive to be done at the cpu level. I like your second one better. thank you!

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