I've seen all three in that use case (and ARM11 cores and earlier where they didn't really make the distinction as overtly). Mainly R and M though.
But the distinction is something like:
M - Thumb2 only, simple two or three stage pipelines typically. Optional everything like selectable (at chip design time) multiply unit that's either 1 or 32 cycles of latency. MPU (if present) only adds protection information, but doesn't remap memory like a full MMU. An ascetic M has something like 12k gates which is insanely low for a 32 bit processor. It mainly competes with AVRs, 8051s, and maybe really low end MIPS if anyone is still using R3000s. In a laptop, I've seen them in power management controllers, bluetooth, and sometimes in WiFi.
R - More powerful than M. Runs Thumb and A32. Clear, deterministic. In order pipeline, tightly coupled memory, and an MPU so that you can still run hard real time cycle counting kind of code twiddling GPIOs carefully, but then also running DSP on the results afterward. I've seen a lot of these in hard disk controllers. They're sort of spiritual successors to the ARM9/7 you know from the DS. Competes with most MIPS.
A - Sort of all over the place. Some are 32bit, some are both 32 and 64. Has a real, page table MMU. Typically run real, big boy kernels like Linux. Competes with Atoms, higher end MIPS (see a trend?) and POWER at the very high end if you squint enough. Typically they're complex enough that you can't cycle count and get deterministic results (longer pipelines, TLB that'll refill 'randomly', cache refills, more complex branch predictor), but give higher overall performance. I think I've seen an A8 as a sound processor? Typically though they're not really a coprocessor, the gate count is too high to make sense.