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An ARM killer from IIT-M?

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Re: An ARM killer from IIT-M?

#61

Post by gsmadhusudan »

happy-go-lucky wrote: post #18

> The landscape is full of thick trees that have set down roots for decades. Bats, deers, and monkeys, seemingly comfortable with the few thousand bicycle-riding students, academics, and staff on campus, are easy to spot. The air, thanks to a recent bout of rains in Chennai, is as good as a hill station In addition to the above description, a picture should have been inserted above or below the paragraph.

http://iglc2018.com/images/iit/4.jpg https://qph.ec.quoracdn.net/main-qimg-2200d147343aa841a43a07... http://2.bp.blogspot.com/_OgX4b2N9a8E/S7OVv7jxhmI/AAAAAAAAAh... http://www.mbaskool.com/2013_images/photography/landscape_na...

We are one of the last refuges of the endangered black buck. The spotted deer and bonnet macaques are more common in India. Odd that a university campus in the middle of a city is a refuge. The pic is that of an albino black buck, an even rarer mutant.

Re: An ARM killer from IIT-M?

#62

Post by LeifCarrotson »

m45t3r wrote: post #52
pedroaraujo wrote: post #29

Earlier quoted context omitted.

That is simply not true. Building a CPU can be "easy" if you want to build something that works. If you want to build something that is power efficient and, at the same time, quite performant, then the complexity of the problem escalates very quickly. Sticking at 30-50 MHz? What is this even supposed to mean? Digital hardware design hardly takes clock speeds into consideration, except during physical implementation i…

> Sticking at 30-50 MHz? What is this even supposed to mean? Digital hardware design hardly takes clock speeds into consideration, except during physical implementation in the later stages of the hardware development. I think what OP means is that you can simulate in software a 30-50MHz version of your own CPU, without having the hardware ready, so you can starting testing if i.e. Linux can boot.

I thought that what OP meant is that if you can only run the simulation for a relatively simple CPU at, say, 1 MHz, you can run and debug firmware for a 30 MHz CPU effectively, even if it's a little annoyingly slow - your 1-second init routine takes 30 seconds, but that's OK. If you have a 1 GHz CPU, whose more complicated architecture can only be simulated at 500 kHz, then a simulation is really tedious. A 20-second boot IRL of, say, Android takes half a day on your simulated processor.

That's not to say there's not someone coming in this morning to step through the overnight simulation they ran, but it's a lot easier to work with when your simulation runs nearer real time.

Re: An ARM killer from IIT-M?

#63

Post by tech2 »

jabl wrote: post #46
bsder wrote: post #28

Earlier quoted context omitted.

> And DEC alpha. I really wish all these "open source" chips would just steal the DEC Alpha microarchitecture and implement it. It's been almost 20 years--even the patents on EV7 should have run out by now. It was a really clean, mostly orthogonal microarchitecture that had most of the really annoying implementation corners filed down. EV5 is a very straightforward chip and maps very well to low power implementations…

IIRC one of those homegrown Chinese HPC chips were rumored to more or less use the Alpha ISA. That being said, I wonder if at this point all the low level software (kernels, toolchains etc.) have bitrotted to the point that you're not buying much, if anything, compared to using RISC-V. And it's not like Alpha doesn't have those irritating ISA idiosyncrasies. E.g. the most crazily relaxed memory model known to man. No…

Regarding the big-endian nature of it: kinda, but also kinda not. Network endianness is generally big, so it'd work well in those instance without needing to do any juggling. Plus (speaking from experience many decades ago on the 68k) reading big-endian memory was so much easier that trying to decipher things in a hex editor on ix86. Though, granted, this is both apocryphal and a minor thing to worry about.

Re: An ARM killer from IIT-M?

#64

Post by [deleted] »

m45t3r wrote: post #52
pedroaraujo wrote: post #29

Earlier quoted context omitted.

That is simply not true. Building a CPU can be "easy" if you want to build something that works. If you want to build something that is power efficient and, at the same time, quite performant, then the complexity of the problem escalates very quickly. Sticking at 30-50 MHz? What is this even supposed to mean? Digital hardware design hardly takes clock speeds into consideration, except during physical implementation i…

> Sticking at 30-50 MHz? What is this even supposed to mean? Digital hardware design hardly takes clock speeds into consideration, except during physical implementation in the later stages of the hardware development. I think what OP means is that you can simulate in software a 30-50MHz version of your own CPU, without having the hardware ready, so you can starting testing if i.e. Linux can boot.

[deleted]

Re: An ARM killer from IIT-M?

#65

Post by raverbashing »

pedroaraujo wrote: post #29
ChuckMcM wrote: post #16

To be honest though building a processor these days is not exactly difficult. That is especially true if you start with someone else's ISA and they have already created a GCC or LLVM back end for it. I was at Sun during the development of SPARC and as part of the Systems group we got to see a lot of the trade offs up front but these days transistors are not nearly so scarce. If you stick to 30 - 50Mhz for your first…

That is simply not true. Building a CPU can be "easy" if you want to build something that works. If you want to build something that is power efficient and, at the same time, quite performant, then the complexity of the problem escalates very quickly. Sticking at 30-50 MHz? What is this even supposed to mean? Digital hardware design hardly takes clock speeds into consideration, except during physical implementation i…

> What is this even supposed to mean? Digital hardware design hardly takes clock speeds into consideration

You purport to correct him and then you drop this phrase, which is questionable at best and wrong at worse.

You do design something that has different clock speeds differently. (Pipelining, power consumption, delays across different parts of the circuit). This is not anything too fancy, this is digital design/IC design 101.

Your post makes a lot less sense than his

Re: An ARM killer from IIT-M?

#66

Post by drudru11 »

0xbear wrote: post #2

ARM can’t be killed at this s point. Positioning themselves as ARM killer would not be the wisest move on anyone’s part.

I agree with this. I was just looking at the microcontroller market, and I can tell you that AVR is going to be around a long time (like PIC).

Re: An ARM killer from IIT-M?

#67

Post by drudru11 »

gsmadhusudan wrote: post #30

As the lead architect of Shakti and the guy who helped kick-start the project, I figure I am owed my 2 cents ! 1. We never positioned it as an ARM killer ! That was the imagination of the reporter who wrote the article. 2. Shakti is not a state only project. Parts of Shakti are funded by the govt, these relate to cores and SoCs needed by the Govt. The defense and strategic sector procurement is huge, runs in the 10s…

Thanks for the clarifications - always good to hear from the source.

I think there are many people waiting for some real RISC-V ISA silicon. The existing chips are really under powered samples at this point. So, this article made me glad to see this announcement.

Re: An ARM killer from IIT-M?

#68

Post by afsina »

gsmadhusudan wrote: post #37
afsina wrote: post #33

Earlier quoted context omitted.

That is why most likely they will not succeed in economical sense. Commercial tech space is just way too fast for governments to follow efficiently.

On the contrary, we started Shakti because our lab can track technology faster than a commercial outfit ! I am an ex-industry architect and a startup CEO who came back to academia started this effort because the pvt sector was moving too slowly wrt CPU research and deployment. Done well govt entities can move really fast once you figure out how to deal with bureaucracy. And we can dream way bigger.

We shall see. Free money has hidden costs.

Re: An ARM killer from IIT-M?

#69

Post by raverbashing »

inteleng wrote: post #43
pedroaraujo wrote: post #29

Earlier quoted context omitted.

That is simply not true. Building a CPU can be "easy" if you want to build something that works. If you want to build something that is power efficient and, at the same time, quite performant, then the complexity of the problem escalates very quickly. Sticking at 30-50 MHz? What is this even supposed to mean? Digital hardware design hardly takes clock speeds into consideration, except during physical implementation i…

I'm not sure why pedroaraujo is being downvoted other than in response to his criticism of HN topcommenter Chuck McManis. Pedro is correct; toy CPUs , like what Chuck mentioned building, are so trivial that undergraduate students can build functioning models of them in a few days or hours. They are quite literally thousands of times less complex than the CPUs (even RISC arches) that are discussed in the article. I al…

> clock speed has absolutely nothing to do with your hardware design until you have written all the HDL, simulated its behavioral characteristics, actually synthesized the logic, completed the analog and I/O components of the design, and are actually preparing for tapeout

So you're going to do all of that without even thinking about your target clock rate? Unlikely

But your comment I can respect, as you explained things politely

> I'm actually quite glad to see another implementation of RISC-V from outside the US. The horde of nearly identical ARM cores on the market is terribly uninspiring.

Totally agree

Re: An ARM killer from IIT-M?

#70

Post by happy-go-lucky »

gsmadhusudan wrote: post #61
happy-go-lucky wrote: post #18

> The landscape is full of thick trees that have set down roots for decades. Bats, deers, and monkeys, seemingly comfortable with the few thousand bicycle-riding students, academics, and staff on campus, are easy to spot. The air, thanks to a recent bout of rains in Chennai, is as good as a hill station In addition to the above description, a picture should have been inserted above or below the paragraph.

http://iglc2018.com/images/iit/4.jpg https://qph.ec.quoracdn.net/main-qimg-2200d147343aa841a43a07... http://2.bp.blogspot.com/_OgX4b2N9a8E/S7OVv7jxhmI/AAAAAAAAAh... http://www.mbaskool.com/2013_images/photography/landscape_na... We are one of the last refuges of the endangered black buck. The spotted deer and bonnet macaques are more common in India. Odd that a university campus in the middle of a city is a refuge. T…

Thank you very much. They're beautiful! An ideal academic environment imo.
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