There was a talk about this on this year's debconf
Delivering Software for Memory Driven Computing
IBM scientists say radical new ‘in-memory’ architecture will speed up computers
131–138 of 138 posts
Re: IBM scientists say radical new ‘in-memory’ architecture will speed up computers
#132So sorry to find this thread on HN while intoxication. I need to write a blogpost about it in a couple of days. In short, these devices are more capable and realizable than most can imagine. Disclaimer: Neuromorphic computing with PCRAM devices is my MSc and future PhD thesis topic.
If only there was room in the margin.
Re: IBM scientists say radical new ‘in-memory’ architecture will speed up computers
#133Earlier quoted context omitted.
Brings to mind images of Conway's Game of Life, with computations moving about a grid of memory as they create and destroy new bits of data.
And that brings to mind http://www.conwaylife.com/w/index.php?title=HashLife , an example (of many) of an algorithmic improvement that gives a way higher speed up than parallellizing and throwing hardware at a problem.
Hashlife is a brilliant algorithm. For anyone not familiar (and vaguely interested in Conway's GOL), highly recommend reading up about it. I found it mildly mindblowing :)
Re: IBM scientists say radical new ‘in-memory’ architecture will speed up computers
#134Earlier quoted context omitted.
The answer is no, but the sad part is, there's no real reason why not. An FPGA isn't really a "gate array," but a huge ensemble of small lookup tables that are made with what amounts to very fast static RAM. If major FPGA manufacturers didn't guard their bitfile formats with their lives, it's possible that entirely new fields of research would have emerged to find new ways to take advantage of the existing hardware i…
> If major FPGA manufacturers didn't guard their bitfile formats with their lives[...] Why do they?
I should say they don't have real reasons, but they have plenty of weak ones. They see their toolchains as part of their competitive advantage, which is weird because FPGA toolchains are some of the most annoying software applications around. The market as a whole could only benefit from additional third party involvement.
Especially at the high end, the manufacturers commonly introduce new hardware constructs -- high-speed transceivers, clock generators, memory controllers, that kind of thing -- and they don't really want to document and disclose the inner workings of these components at a level that would allow third parties to write tools for them. It could potentially take a non-trivial amount of documentation and customer support work. Meanwhile they want to preserve their trade secrets, and they also don't want to attract infringement suits from either patent trolls or legitimate competitors. Disclosure of bitfile formats would open those particular kimonos a bit too wide for comfort. This is largely why Linux users can only get GPU support via binary blobs.
At the low end, some good reverse-engineering progress has been made by people like Clifford Wolf on the Lattice parts. This work is certainly important, but as long as there's reasonably rapid technological progress on the hardware side, reverse engineering is never going to be enough to sustain a healthy third-party tools industry.
It's a real shame. Imagine how far we'd (not) have come if Intel and Motorola had walled off their instruction sets...
Re: IBM scientists say radical new ‘in-memory’ architecture will speed up computers
#135Earlier quoted context omitted.
HN has only been around since 2007
Ambiguous language. I thank what was being implied is that it was the first occurrence of that type of article on HN , not that the article was the first ever about memristers and was posted to HN.
Not really that relevant to the ongoing point of the age of memristor articles then.
Re: IBM scientists say radical new ‘in-memory’ architecture will speed up computers
#136Earlier quoted context omitted.
Feynman also ranted about how much processing within the memory would speed computing in the 80's. He challenged those "computer scientists" to figure it out :P .... this lecture: http://cse.unl.edu/~seth/434/Web%20Links%20and%20Docs/Feynma...
Very insightful post. Thanks for that. I skimmed the paper and enjoyed the illustrations, and the photos at the end :). So Memristors are about reversible gates instead of non-reversible NAND gates?
I think what he implied was that more reliable calculations would come from reversible gates, though they'd ultimately be slower. The speed being one of the main reasons they weren't used in processor design. One of the solutions for that problem was the parallel design that could compensate for the slowdown of individual calculations by the ability to run many at the same time, and of course the increased rate of transmission by performing the calculations right within the memory instead of the added latency of fetching and storing values every values and performing every calculation synchronously.
So I think it's more that memristors would be a solution that allows the use of reversible gates making for more reliable processors. If anybody else has any better insight, fire away.
Re: IBM scientists say radical new ‘in-memory’ architecture will speed up computers
#137Earlier quoted context omitted.
The answer is no, but the sad part is, there's no real reason why not. An FPGA isn't really a "gate array," but a huge ensemble of small lookup tables that are made with what amounts to very fast static RAM. If major FPGA manufacturers didn't guard their bitfile formats with their lives, it's possible that entirely new fields of research would have emerged to find new ways to take advantage of the existing hardware i…
Hmmmm. I wonder how expensive it would be to make a really really tiny FPGA with a few tens of cells in it. As in, I realize chip design is expensive and crazy complicated, but small runs are only around $5k or so. I'm wondering if FPGAs manufacturing has similar costs - or at least similar-ish enough to be potentially interesting. If you could go from zero to tiny prototype FPGA with 5 or 6 figures, you might just b…
Here are a couple of articles about a homebrew FPGA (only one logic cell, but it's step in your direction).
Re: IBM scientists say radical new ‘in-memory’ architecture will speed up computers
#138Earlier quoted context omitted.
Hmmmm. I wonder how expensive it would be to make a really really tiny FPGA with a few tens of cells in it. As in, I realize chip design is expensive and crazy complicated, but small runs are only around $5k or so. I'm wondering if FPGAs manufacturing has similar costs - or at least similar-ish enough to be potentially interesting. If you could go from zero to tiny prototype FPGA with 5 or 6 figures, you might just b…
Here are a couple of articles about a homebrew FPGA (only one logic cell, but it's step in your direction). https://hackaday.com/2012/09/20/homebrew-fpgas/ http://blog.notdot.net/2012/10/Build-your-own-FPGA
ooo, interesting. Thanks for this!