Earlier quoted context omitted.
I've been thinking of something similar recently - to extend your idea slightly, why couldn't the flashing of the FPGA happen per tick? Thus at every tick your FPGA could become entirely different hardware, tailored to whatever task is required at that tick.
Well, flashing is pretty slow compared to modern computers. You have to load it from flash (no pun) memory and Altera are the only ones (AFAIK) that support only changing subsections. (Which could be great because you can change only a half or quarter of your FPGA with new logic units while the others keep running.) Also, you'd have to know what you'd need... before you need it. Which is kind of impossible. By time y…
Yes, it's the predictive aspect of it that I've struggled with also! I understand there are technical limitations at present, was just trying to extend the idea beyond what's currently possible to see if it might be interesting.