Intel Gears Up for FPGA Push • Hacker News Board

Re: Intel Gears Up for FPGA Push

#81

Post by chillingeffect » Tue, Oct 03, 2017, 3:19 PM UTC

nakedrobot2 wrote: post #47

nimish wrote: post #44

Tooling tooling tooling. FPGA hardware is cool but the tooling fucking sucks. Like stepping back into the time where you needed to pay thousands of dollars to get decent compilers and debuggers. The ability for anyone to develop software for CPUs at zero-cost is an amazing freedom. You literally cannot do that on certain fpgas--not only do they cost thousands, so do the tools to actually create a working design. Unti…

FPGA's are extremely powerful, but the toolchain is absolute dog shit. Xilinx, shame on you. Intel, will you change anything here? The compound problem of this in reality is that finding the right people who have the right strain of semi-insanity to do this really well, is very slim. And most of them are tied up with a massive salary from some aerospace company such as Raytheon, GE, Honeywell, or someone like Philips…

hahaah yes, i just installed a Xilinx tool and they had me watch an "Installer training Video."

The gist of which is you can now actually uncheck products you don't need to install, preventing them from being installed.

Re: Intel Gears Up for FPGA Push

#82

Post by pm215 » Tue, Oct 03, 2017, 3:24 PM UTC

bradfa wrote: post #72

pm215 wrote: post #22

Earlier quoted context omitted.

The underlying problem here is that the cost of making an SoC is enormous. So to make, say, an ARM desktop class machine you have only a few choices: 1) Make your own SoC designed for the purpose. You can tailor it to meet your requirements precisely, but given the low volumes you'll be selling, your system will be at least $10,000 a box, likely more. 2) Use a designed-for-mobile SoC. This will hit your $200-$300 pri…

Raptor Computing Systems will sell you a 4 core POWER9 CPU for $340 each [1]. A desktop mobo with the kinds of features discussed shouldn't be more than a few hundred dollars if slimmed down to one socket and a reasonable but limited set of peripherals (the Talos mobos go a bit over the top with features and hence are >$1k). Someone just has to design one, which is not easy or inexpensive, then hope that developers a…

It's a few hundred dollars if you have the market volume to sell it at that price. IBM have the volume (presumably mostly for servers) so they can do it. You can't spend the amount it costs to make a new SoC based only on the "hope" that people buy it; you need a business plan that says where the volume will come from, and there aren't enough customers for a developer box alone to provide that volume, so the dev box uses will always be a sideline from something else.

Re: Intel Gears Up for FPGA Push

#83

Post by murph-almighty » Tue, Oct 03, 2017, 3:28 PM UTC

Does this mean we can develop using some not-Xilinx proprietary crapware?

Re: Intel Gears Up for FPGA Push

#84

Post by morphle » Tue, Oct 03, 2017, 3:41 PM UTC

selimthegrim wrote: post #69

AriaMinaei wrote: post #67

Earlier quoted context omitted.

I remember a talk by Alan Kay where he mentioned a number of problems commonly solved serially, such as 2D layout and typesetting, and then he demonstrated a parallel algorithm for each problem. If I remember and understand correctly (I may not), one of his points was that such algorithms can become trivially implementable in a dynamic language and would run fast too, if the hardware supported some of the primitives…

Do you remember the title or have a link?

Alan Kay gave a talk at Qualcomm in San Diego, on October 30, 2013. "Is it really complex or did we just make it complicated?" https://vimeo.com/82301919

Re: Intel Gears Up for FPGA Push

#85

Post by Symmetry » Tue, Oct 03, 2017, 3:45 PM UTC

simias wrote: post #45

nimish wrote: post #44

Tooling tooling tooling. FPGA hardware is cool but the tooling fucking sucks. Like stepping back into the time where you needed to pay thousands of dollars to get decent compilers and debuggers. The ability for anyone to develop software for CPUs at zero-cost is an amazing freedom. You literally cannot do that on certain fpgas--not only do they cost thousands, so do the tools to actually create a working design. Unti…

I dream of a GCC/LLVM for FPGAs. I'm not holding my breath for Intel to help with that though.

There are some people working on that, for example:

http://www.clash-lang.org/

Re: Intel Gears Up for FPGA Push

#86

Post by AriaMinaei » Tue, Oct 03, 2017, 3:52 PM UTC

morphle wrote: post #84

selimthegrim wrote: post #69

Earlier quoted context omitted.

Do you remember the title or have a link?

Alan Kay gave a talk at Qualcomm in San Diego, on October 30, 2013. "Is it really complex or did we just make it complicated?" https://vimeo.com/82301919

Was just going to post that link. It's a very nice talk. Highly recommended!

Re: Intel Gears Up for FPGA Push

#87

Post by justinjlynn » Tue, Oct 03, 2017, 3:56 PM UTC

BoorishBears wrote: post #71

amelius wrote: post #42

Earlier quoted context omitted.

Otoh, he could have just written "I've found this patent" and nobody would have known he was the author.

But no one would know the author was referencing his own patent and thus knowledgable about the subject if one wanted to conversate on it

It's still terrible opsec. Of course, as always, it depends on the threat model. Still, linkage and contamination are deadly - why give up more information than absolutely necessary for your adversar[y|ies] to use against you in the future. All it takes is one mistake or a few 'almost mistakes'.

Re: Intel Gears Up for FPGA Push

#88

Post by aeruder » Tue, Oct 03, 2017, 3:57 PM UTC

simias wrote: post #70

aeruder wrote: post #65

Earlier quoted context omitted.

C (or really any traditional programming language) doesn't really map to an FPGA. There are some compilers out there that attempt to convert traditional C code to state machines for FPGAs, but FPGAs are really a completely different paradigm. You're actually describing digital logic, not a sequence of steps. That being said, there are soft-processors that have been written in VHDL/Verilog and can be incorporated into…

Oh that's not what I was implying, sorry for the confusion. I meant an open source, portable HDL compiler/synthesizer like what GCC/LLVM are for software. As the parent and many others point out in this thread the tooling is a really sore point for FPGA development. It's always big, clunky, often buggy closed source applications (often running on an unhealthy dose of Tcl scripts cobbled together). And of course if yo…

Understood, and I totally agree that it is an industry ready for some shakeup.

I used to work for a large defense contractor doing FPGA work, and we really went out of our way to try to stick to 100% VHDL to attempt to avoid vendor lock-in. This meant things like writing block ram HDL in a way that it would be inferred by the synthesis tool to use the block ram (and not synthesize out of a bunch of LUTs).

It was a constant struggle to keep things synthesizing correctly. We mostly standardized on using Synopsys Synplify Pro for vendor-neutral synthesis and then using the Altera/Xilinx backend tools for place and route, etc. But even then, we regularly had to whitelist certain good versions of Synopsis' tools.

It was possible to do this with the vendor-specific synthesis tools too, but it was still a massive effort to check that primitives synthesized into the correct elements across different parts/vendors. Ugh, do not miss it.

Re: Intel Gears Up for FPGA Push

#89

Post by BoorishBears » Tue, Oct 03, 2017, 3:58 PM UTC

justinjlynn wrote: post #87

BoorishBears wrote: post #71

Earlier quoted context omitted.

But no one would know the author was referencing his own patent and thus knowledgable about the subject if one wanted to conversate on it

It's still terrible opsec. Of course, as always, it depends on the threat model. Still, linkage and contamination are deadly - why give up more information than absolutely necessary for your adversar[y|ies] to use against you in the future. All it takes is one mistake or a few 'almost mistakes'.

What does it have to do with opsec?

Re: Intel Gears Up for FPGA Push

#90

Post by ethbro » Tue, Oct 03, 2017, 3:59 PM UTC

gcp wrote: post #78

aj7 wrote: post #73

Earlier quoted context omitted.

The fact that you don't is an indication of its true value.

I got a Xilinx Spartan DEV board sitting in a drawer too. The board is great but Xilinx's tooling has negative value for me, so it'll stay there. Tooling is 100% the thing keeping FPGAs back.

As far as I can tell, it's an economics problem.

The big consumers of FPGAs don't care if the tooling is terrible, because they're coming from 80s development environments and practices and can afford to dedicate 50-person teams to the job function.

Smaller companies won't touch it because it's terrible, and the vendors won't improve it because there's no demonstrated market for improvements.