I'm not surprised that going back to 3Gbps works; modern high frequency signaling is so close to the boundaries of what works that even things like the length of the SATA cable and how it's oriented, and what temperature components are at, can mean the difference between a working link and one that fails when the right sequence of bits gets sent. DTLE is a way of tuning the transmitter output so that when the signal gets received at the other end, it's as "clear" as possible.
Even early SDRAM controllers had similar tunable settings for clock delays and such, because different DIMMs may vary slightly --- upon POST, the BIOS would set all the settings to nominal values, then nudge each one in one direction while reading/writing pathological data until errors occurred; then nudge them in the other direction until errors occurred, and finally settle on the average of the two extremes. I suspect a similar process needs to be done here, and if you reverse-engineered the BIOS further you would find the algorithm to do it.
More interesting information on DTLE "discrete time linear equalization" here:
http://cc.ee.ntu.edu.tw/~rbwu/rapid_content/course/highspeed...
Big kudos to the Purism folks for trying to figure these things out. And big fuckings to Intel for keeping this stuff NDA'd --- it only makes it harder for those trying to buy and use your products (I hope someone leaks it all eventually...)