Intel Skylake/Kaby Lake processors: broken hyper-threading
181–190 of 278 posts
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#182Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#183Earlier quoted context omitted.
But that doesn't mean you necessarily get to keep the affected feature - the only 'work-around' might be to disable it. Consider TSX on Haswell and Broadwell, where Intel had to disable the whole feature because of a bug. And of course there was the 486 FP bug which couldn't be fixed by any kind of microcode update. If Intel had to completely disable hyperthreading in Skylake and Kabylake that would make the premium…
you mean i3 and i7. despite what cpuinfo tells you, no HT in i5. and my previous comment was ironic :)
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#184My CPU (6th generation i5) died last week. RIP. I installed debian 9, installed virtualbox, vagrant, setup a clean development machine for myself, everything took 4 hours to finish. I reboot the virtual machine, and boom, there was a kernel panic which I sadly don't remember exactly / didn't take a picture of. After I rebooted the machine, and opened terminal, the system froze. The cursor wouldn't move. Reboot again,…
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#185Well, at least Intel acknowledges, documents and finally fixes these CPU bugs (via microcode updates). AMD on the other hand doesn't even acknowledge an issue when multiple customers report problems. See this Ryzen bug: https://community.amd.com/thread/215773
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#186Earlier quoted context omitted.
The problem with finding a physics bug is that it's liable to be amplifiable. Break conservation laws just a little bit and suddenly you have potential for exponential runaway leading to an unplanned reality excursion, and say goodbye to your light-cone.
Well, by definition the behaviour would be undefined so could go any which way. ;) Modern day VM software has various levels of exception checking, and code to catch/mitigate/etc when bugs crop up. So, a universe-capable simulator might have any kind of behaviour if/when a bug occurs. It doesn't need to be an unbounded, runaway scenario. :)
It probably happens more often than we imagine ;-)
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#187The problem description is short and scary: Problem: Under complex micro-architectural conditions, short loops of less than 64 instructions that use AH, BH, CH or DH registers as well as their corresponding wider register (e.g. RAX, EAX or AX for AH) may cause unpredictable system behavior. This can only happen when both logical processors on the same physical processor are active. I wonder how many users have experi…
A few past lives ago, I used to work on the AIX kernel at IBM. I once spent a few weeks poring through trace data trying to investigate a very mysterious cache-aligned memory corruption induced by a memory stress test. Our trace data was quite comprehensive, and is always turned on due to its very low overhead. It was concerning enough (and took me long enough) that it eventually sucked in the rest of my team to aid…
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#188How does one get new microcode on Windows? Is that what the Intel Chipset drivers are? And is the microcode fix available for non-Linux systems yet?
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#189Earlier quoted context omitted.
It wouldn't be a big deal if this was just software, but the fact that Intel allowed a PROCESSOR bug to be reported, tested, and fixed without telling anyone that the bug actually exists is honestly horrible. You can't just let CPU bugs under the run since it can throw the stability and reliability of the entire system into question. The people that reported it shouldn't have to dig through Intel microcode updates an…
Do we have any evidence that that's where Intel even learned about the bug?
Re: Intel Skylake/Kaby Lake processors: broken hyper-threading
#190The problem description is short and scary: Problem: Under complex micro-architectural conditions, short loops of less than 64 instructions that use AH, BH, CH or DH registers as well as their corresponding wider register (e.g. RAX, EAX or AX for AH) may cause unpredictable system behavior. This can only happen when both logical processors on the same physical processor are active. I wonder how many users have experi…