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Intel fires warning shots at Microsoft, says x86 emulation is a patent minefield

arstechnica.com

231–234 of 234 posts

Re: Intel fires warning shots at Microsoft, says x86 emulation is a patent minefield

#231
post #230

Earlier quoted context omitted.

Intel doesnt let anyone else use their fabs.

sure they do, Intel manufactured FPGAs for a long time before buying altera

I don't think FPGA's count in this context but I did a quick search on Intel fabs and it looks like I'm wrong anyway: https://arstechnica.com/gadgets/2016/08/intel-will-allow-arm...

Re: Intel fires warning shots at Microsoft, says x86 emulation is a patent minefield

#232
post #105
post #86

Earlier quoted context omitted.

> All on non-Intel foundry processes. That was unimaginable 10 years ago. Not really. 15 years ago, AMD was outperforming Intel at a lower price.

That was not because of foundry process, but because of better architecture. Intel was leading or tied at process width and clock speed the whole time.

AMD always ran hotter. They were always about the same in technolgy level, just marketed differently because of design choices. Horses for courses.

Re: Intel fires warning shots at Microsoft, says x86 emulation is a patent minefield

#233
post #73
post #63

Earlier quoted context omitted.

No. If they're anything like the Itanium ISA patents, then Intel owns the rights to the instructions themselves and their meanings. Emulation would be infringing.

When it's for the matter of compatibility , are patent laws applicable?

Yes; compatibility necessities are functional rather than expressive and therefore an exception to copyright protection. But patents are about making monopolies on functionality; a compatibility exception would undermine the whole point.

Re: Intel fires warning shots at Microsoft, says x86 emulation is a patent minefield

#234

Earlier quoted context omitted.

Almost everything that you described is microarchitectural, and not tied to the ISA.

> Almost everything that you described is microarchitectural, and not tied to the ISA. They listed these features 'strong memory ordering', '(no) branch delay slots', '(no) stack windows', 'good i-cache efficiency through the use of two-address code and memory operands'. Every single one of those is a property of the ISA - the instruction set, its semantics and encoding - not the implementation. Which do you think is…

strong memory ordering is a contract. There is nothing intrinsic about the ISA, or its virtues, that dictates the ordering one way or the other. It is entirely guided by what the vendor wants to support. x86's ordering is similar to TSO in SPARC, which uses a RISC like ISA. The ordering is described as a part of the ISA, but any ISA can implement a strong ordering (at the risk of performance losses) if they want to.

i-cache efficiency: Again implementation specific. Efficiency is entirely a result of implementation, isn't it ?

no branch delay slot: Yes, this is a part of the ISA. My point though was that it is uncommon enough that I wouldn't call it a great virtue of x86 per se.

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