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Darpa Funds Development of New Type of Processor

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Re: Darpa Funds Development of New Type of Processor

#3

"Darpa Funds Development of New Type of Processor: Worlds First Non-Von-Neumann " https://en.wikipedia.org/wiki/Harvard_architecture ?

Was my thought as well "What? AVR are harvard architecture and I can buy them for 0.1$". But after looking, apparently it is more linked to new parallelism paradigms:

> "This non-von-Neumann approach allows one big map that can be accessed by many processors at the same time, each using its own local scratch-pad memory while simultaneously performing scatter-and-gather operations across global memory."

Re: Darpa Funds Development of New Type of Processor

#5
What does the memory interface look like for this? None of the papers I can find indicate how you can get so much parallelism out of the CPU memory interface.

An interesting approach to non-Von Neumann computing is to put ALUs in memory, to take advantage of the fact that DRAMs have far more internal bandwidth than what is exposed in traditional systems: http://researcher.ibm.com/researcher/files/us-leejinho/tvlsi....

Re: Darpa Funds Development of New Type of Processor

#9
post #5

What does the memory interface look like for this? None of the papers I can find indicate how you can get so much parallelism out of the CPU memory interface. An interesting approach to non-Von Neumann computing is to put ALUs in memory, to take advantage of the fact that DRAMs have far more internal bandwidth than what is exposed in traditional systems: http://researcher.ibm.com/researcher/files/us-leejinho/tvlsi...…

Manufacturing logic on the same wafer as DRAM is difficult since the processes are so different. On the other hand, manufacturing on separate dies and connecting with an interposer or TSVs gets you tremendous bandwidth and relatively low latency; this is how some newer generation graphics memory is implemented (see https://en.m.wikipedia.org/wiki/High_Bandwidth_Memory).
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