31–40 of 48 posts
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Lol, that's because it's about ARMv6. She even points it out in Part 1 or so (not sure where but I saw it somewhere). If you wanna include all differences of ARM that would be a long tutorial.
I think you'll find the only reference to v6 is where the register names are explained, e.g. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
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I think you'll find the only reference to v6 is where the register names are explained, e.g. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
You do realise you are comparing 32 bit ARM and 64 bit ARM, which are very different ISAs?
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I think you'll find the only reference to v6 is where the register names are explained, e.g. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....
You do realise you are comparing 32 bit ARM and 64 bit ARM, which are very different ISAs?
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Since you ask, I use lots of assembly level programming for digital audio signal processing. Some ARM instructions offer special DSP specific features like saturation and fractional arithmetic that have no equivalent int C, so it justifies using assembly. Smaller ARM cores without NEON offer some kind of miniature SIMD by operating on two 16-bit or four 8bit numbers, these can speed up things as well. To take full ad…
I've also been working with DSP processors in audio processing. The only time I've used actual inline assembly was storing stack pointer to measure stack usage. For saturating arithmetic and other stuff we used compiler intrinsics, which freed us from handling register allocation, stack management etc by hand. On that processor there weren't special instructions for saturating arithmetic but a flag was used instead,…
What do they do? I haven't seen anything like this before.
I see some explanation in https://azeria-labs.com/arm-conditional-execution-and-branch... but the reason why branching must work this way isn't explained.
edit: I see "Branch with Exchange" switches the processor from ARM to Thumb in http://www.embedded.com/electronics-blogs/beginner-s-corner/.... But I don't see why switching processor modes must happen on branch instructions.
Some of the arm instruction set manuals seem harder to come by than others. Recently I reverse engineered one of the firmwares of the ImmersionRC Vortex 150 racing quadcopter (it uses an stm32f3 chip, arm cortex instruction set). It was pretty hard to come by a copy of the full instruction set manual - i just assumed that kind of thing would be a quick google away. Eventually i got there and made my changes but it wa…
What are you talking about??? https://static.docs.arm.com/ddi0403/e/DDI0403E_B_armv7m_arm.... http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/BA... There is also the old cheat sheet: http://users.ece.utexas.edu/~valvano/Volume1/QuickReferenceC...
I think you've inadvertently just helped make my case for me.
I don't have a link to share unfortunately, the only way i could get access was by going to ST directly.
What's with the branch instructions "Branch with Link" and "Branch with Exchange"? What do they do? I haven't seen anything like this before. I see some explanation in https://azeria-labs.com/arm-conditional-execution-and-branch... but the reason why branching must work this way isn't explained. edit: I see "Branch with Exchange" switches the processor from ARM to Thumb in http://www.embedded.com/electronics-blogs/be…
There are branching instructions that can't change instruction sets for two reasons: 1. A direct branch can have more range if you can assume it's going to a 4-byte aligned address. 2. For compatibility with code written for ARM7DI and other really old pre-thumb processors. Since the original direct branch instructions ignored the bottom two bits of the target address, new direct branch instructions were added rather than change the behavior of the existing ones.
What's with the branch instructions "Branch with Link" and "Branch with Exchange"? What do they do? I haven't seen anything like this before. I see some explanation in https://azeria-labs.com/arm-conditional-execution-and-branch... but the reason why branching must work this way isn't explained. edit: I see "Branch with Exchange" switches the processor from ARM to Thumb in http://www.embedded.com/electronics-blogs/be…
This is distinct from x86 32 vs 64 bit and ARM 32 vs 64 bit: in both those cases there's really a different processor mode with extra registers and so forth, and switchover is correspondingly more involved.
Some of the arm instruction set manuals seem harder to come by than others. Recently I reverse engineered one of the firmwares of the ImmersionRC Vortex 150 racing quadcopter (it uses an stm32f3 chip, arm cortex instruction set). It was pretty hard to come by a copy of the full instruction set manual - i just assumed that kind of thing would be a quick google away. Eventually i got there and made my changes but it wa…
For documentation of the devices in a particular SoC you'll need the reference manual from the SoC manufacturer -- they of course vary in how easy it is to find those docs.
I'm only a couple of pages in but already a lot of this guide is incorrect for ARMV8-A (A64). Much is different, e.g. no thumb mode, no directly accessible program counter, no load multiple, no PUSH/POP, different stack pointer, etc. Looks good if you're interested in older ARM ISAs, which is probably more applicable for IoT etc.