Intel releases the last Itanium chip, the 9700
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Re: Intel releases the last Itanium chip, the 9700
#2The Itanium is a noteworthy example of what happens when one designs an architecture exclusively for parallelism to the exclusion of all else, and leaves all instruction scheduling to the compiler. The performance was great when software could take advantage of the parallelism, but horrible otherwise, since the processor would still be fetching bundles of 3 instructions (16 bytes each!) but only 1/3 of them would be anything other than NOPs, effectively making each instruction a ridiculously-cache-bloating 16 bytes long.
I suppose a similar analogy would be doing everything in x86 with SIMD instructions and not using the scalar set at all.
Re: Intel releases the last Itanium chip, the 9700
#3[deleted]
Re: Intel releases the last Itanium chip, the 9700
#4We would probably all be working with Itanium servers if not for AMD introducing 64 bit x86. I believe that also accelerated Linux adoption and the decline of all the commercial Unix platforms.
Good to see AMD on the rise again. I appreciate their role in heading off Itanium.
Re: Intel releases the last Itanium chip, the 9700
#5The Itanium is a noteworthy example of what happens when one designs an architecture exclusively for parallelism to the exclusion of all else, and leaves all instruction scheduling to the compiler. The performance was great when software could take advantage of the parallelism, but horrible otherwise, since the processor would still be fetching bundles of 3 instructions (16 bytes each!) but only 1/3 of them would be…
> I suppose a similar analogy would be doing everything in x86 with SIMD instructions and not using the scalar set at all.
With ever wider SIMD units this is actually happening to some extent. With AVX512 (e.g. on KNL) you can do 64 operations (single precision FLOPs) in vector units in the same amount of time as you can do 1 scalar operation. Combined with the low clock speed of the KNL, you really don't want to be doing scalar operations if you care at all about performance. Of course SIMD isn't the same as VLIW, since the operation you're doing has to be the same in all vector lanes, but with masking support in AVX512, it is getting a little closer to that.
Also compilers have gotten quite a bit smarter and with hardware die shrinks taking longer, I wouldn't be at all surprised if VLIW ISAs were to make a comeback. I guess the Itanium was a bit ahead of its time.
Re: Intel releases the last Itanium chip, the 9700
#6The Itanium is a noteworthy example of what happens when one designs an architecture exclusively for parallelism to the exclusion of all else, and leaves all instruction scheduling to the compiler. The performance was great when software could take advantage of the parallelism, but horrible otherwise, since the processor would still be fetching bundles of 3 instructions (16 bytes each!) but only 1/3 of them would be…
ILP specifically which, as it turned out was largely giving way to TLP in any case. I started writing a lesson from Itanium piece a while back. Maybe I should dust it off. (I followed Itanium pretty closely for a long time while I was an analyst.)
Re: Intel releases the last Itanium chip, the 9700
#7The Itanium is a noteworthy example of what happens when one designs an architecture exclusively for parallelism to the exclusion of all else, and leaves all instruction scheduling to the compiler. The performance was great when software could take advantage of the parallelism, but horrible otherwise, since the processor would still be fetching bundles of 3 instructions (16 bytes each!) but only 1/3 of them would be…
> I suppose a similar analogy would be doing everything in x86 with SIMD instructions and not using the scalar set at all. With ever wider SIMD units this is actually happening to some extent. With AVX512 (e.g. on KNL) you can do 64 operations (single precision FLOPs) in vector units in the same amount of time as you can do 1 scalar operation. Combined with the low clock speed of the KNL, you really don't want to be…
This, recent compiler advances in the past two decades have actually made VLIW somewhat tractable, but since the memory hierarchy and data movement wall consumes most of the power nowadays, the benefits of VLIW are mitigated.
Re: Intel releases the last Itanium chip, the 9700
#8We would probably all be working with Itanium servers if not for AMD introducing 64 bit x86. I believe that also accelerated Linux adoption and the decline of all the commercial Unix platforms. Good to see AMD on the rise again. I appreciate their role in heading off Itanium.
What makes you think it wouldn't have been POWER? Or SPARC? They were both way more popular than PA-RISC.
Re: Intel releases the last Itanium chip, the 9700
#9Question seeking to understand - Why would anyone buy a tech component product that is explicitly called out as last of its kind?
Re: Intel releases the last Itanium chip, the 9700
#10We would probably all be working with Itanium servers if not for AMD introducing 64 bit x86. I believe that also accelerated Linux adoption and the decline of all the commercial Unix platforms. Good to see AMD on the rise again. I appreciate their role in heading off Itanium.
Had x86_64 not been released, I also think we'd see a more diverse set of serverside chips as well, such as SPARC and POWER. There wouldn't have been an obvious dominance in the marketplace of a single architecture.
Also, had it not been released, we'd probably have seen a larger fracturing of the laptop CPU market with a broader switch to ARM64.
In a sense, because AMD forced Intel's hand in supporting x86_64, they actually helped Intel have even more dominance in the market with an architecture that spans laptops to server work horses. We developers barely need to lift a finger in targeting either.