DDR5 memory is on its way, twice as fast as DDR4 • Hacker News Board

Re: DDR5 memory is on its way, twice as fast as DDR4

#71

Post by adrianratnapala » Fri, Mar 31, 2017, 7:12 PM UTC

trey-jones wrote: post #6

So, it's been a while since I tinkered with hardware, but I'm making the blind assumption that although the bus speed is twice as fast as DDR4, there is also twice the read latency, as has always been the case with DDR memory, meaning the net read latency improvement is basically nil. Of course we expect every generation of Double Data Rate memory to double the data rate. But it's always been a bit misleading to say…

All this means is that we should stop thinking of this stuff as RAM. Only the L1 cache is really RAM. Everything else is just a kind of fast, volatile, solid state disk that just happens to share an address space with the RAM.

Re: DDR5 memory is on its way, twice as fast as DDR4

#72

Post by Retric » Fri, Mar 31, 2017, 7:18 PM UTC

gatsby99 wrote: post #69

Retric wrote: post #67

Earlier quoted context omitted.

Traces only go from CPU pin to Module, latency includes from memory controller CPU pin, CPU pin to PCB, PCB to module, module to RAM chip edge, ram chip edge to actual memory location. Here is a picture, from the center of the CPU, to the bottom edge of the furthest part of the DIM then up. http://harddiskdirect.com/media/catalog/product/cache/1/imag... PS: A DIMM is just over 5 inches wide and 0.7 inches tall so if…

You don't know what you are talking about. Memory controllers are typically onchip.

If by on chip you mean on CPU I agree: https://en.wikipedia.org/wiki/Memory_controller

But, that's part of the CPU packaging, a signal needs to get to these pins on the bottom of the CPU and that takes time.

Re: DDR5 memory is on its way, twice as fast as DDR4

#73

Post by jjoonathan » Sat, Apr 01, 2017, 12:51 AM UTC

Retric wrote: post #47

jjoonathan wrote: post #36

Earlier quoted context omitted.

tCL is (very) roughly the RAM equivalent of sequential access time. I'm talking random access time, tRAS, which includes closing the last row (precharging the diff amps) and opening the next (waiting for the amps to stabilize). It's called Random Access Memory, so I think it's more fair to judge it by its random access time.

tCL is very much a round trip latency not just sequential access. If you want sequential access 4 times you can pay for tCL once. https://www.altera.com/ja_JP/pdfs/literature/hb/external-mem... DDR is not really setup for random access, because it's setup for talking to L2/L3 cache not registers. tRAS ~= tCL + tRCD + tRP which kind of but not exactly exactly what you want for random access.

Yes, tCL is a round trip time for accessing an already open row, and it puts a sharp upper bound of ~5ns on propagation delay. Random access time, approximated by tRAS, is still ~50ns. You contend that tCL is the bigger problem, I contend that tRAS is the bigger problem. The key statistic is , which I haven't been able to find easy values for.

I don't understand your argument that the L2 and L3 caches tip the balance in favor of . If anything, I'd expect them to do the opposite, because the SRAM and DRAM both aim to exploit locality, meaning that better L2 and L3 caches would reduce #CAS faster than #RAS. Of course, armchair reasoning about such complex systems as memory controllers and caches can only go so far, so I wouldn't be shocked to be wrong, but I would certainly demand actual statistics before changing my view.

Re: DDR5 memory is on its way, twice as fast as DDR4

#74

Post by koverstreet » Sat, Apr 01, 2017, 5:44 AM UTC

gatsby99 wrote: post #69

Retric wrote: post #67

Earlier quoted context omitted.

Traces only go from CPU pin to Module, latency includes from memory controller CPU pin, CPU pin to PCB, PCB to module, module to RAM chip edge, ram chip edge to actual memory location. Here is a picture, from the center of the CPU, to the bottom edge of the furthest part of the DIM then up. http://harddiskdirect.com/media/catalog/product/cache/1/imag... PS: A DIMM is just over 5 inches wide and 0.7 inches tall so if…

You don't know what you are talking about. Memory controllers are typically onchip.

"You don't know what you are talking about" is not a great response to someone who's writing more substantive posts than you.