Earlier quoted context omitted.
Latency is limited by the speed of electricity which is a large fraction of the speed of light, so unless you move DDR closer to the CPU it physically can't get 2x as fast... ever. light speed * 0.951 (electricity) / 2 (round trip) / 2 feet (CPU to furthest RAM chip along a wire) ~= 250 million cycles per second. However, cache is now huge. So, it's latency is usually less of an issue than sequential reads/writes and…
Out of curiosity, why did you ballpark the length of the wire to "2 feet" (close to an order of magnitude high, way under 1 digit of precision) but specify the wave propagation speed along that wire to one part in a thousand (way more precision than appropriate: line capacitance changes significantly with trace width, pcb thickness to ground plane, pcb composition, etc...)? You're point isn't invalid but it's sort of…
Anyway, if you actually trace the furthest bit of a ram chip to the CPU it's a longer path than you might think > 1 foot but As to my point tCL is a round trip latency and actually not that far from optimal. DDR is not designed for pure random access so much as cheap access to lot's of ram so yes there are many trade offs, but they are more reasonable when your close to hard limits.