This is awesome, thanks for sharing it.
It pains me though that you haven't experienced a 'real' logic analyzer (and that is in quotes because they are all real but originally they were different).
So originally, the way the logic analyzer worked was that you had a 'clock' module and 'data' lines. The clock module fed a clock signal into analyzer and you told it so sample the data lines on the rising, falling, or both clock edges. It was done this way because all digital logic works on the clock edges. You could also 'oversample' where you ran the system clock through a clock doubler or quadrupler or octupler and used that as your clock source. That would let you look at a signal multiple times. Most of the doubler circuit patents[1] have expired so using them/building them is fine.
Given that setup you could analyze your logic using the clock the logic was using and everything just worked. To translate back into 'real' time you either had to measure the logic's clock or annotate the samples with a free running clock built into the analyzer.
What you have built, and a lot of people have experienced on things like the Rigol scope and elsewhere, is more like a 'digital oscilloscope' where you digitally sample the inputs at a given frequency. This is fine for doing serial bus decoding (especially if you can sample at 16x the bus frequency) but it doesn't help on logic analysis if your tracking down timing issues. Because the signal may have changed state at any time between the sampling interval you can't check setup or hold times accurately.
[1] https://www.google.com/patents/US5111066 as an example