131–140 of 169 posts
I think Naples is a very exciting development, because: - 1S/2S is obviously where the pie is. Few servers are 4S. - 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas - First x86 server platform with SHA1/2 acceleration - 128 PCIe lanes in a 1S system is unprecedented All in all Naples seems like a very interesting platform for throughput-intensive…
Cool man...
> SHA1 IN 2017
Uhhh, yeah, cool man
I think Naples is a very exciting development, because: - 1S/2S is obviously where the pie is. Few servers are 4S. - 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas - First x86 server platform with SHA1/2 acceleration - 128 PCIe lanes in a 1S system is unprecedented All in all Naples seems like a very interesting platform for throughput-intensive…
My shallow understanding of big servers and IBM Z series amounted to "lots of dedicated IO processors". Seems like "mainstream" caught up with big blue.
Every mainframe interface is basically an offload interface.. "computers" DMAing and processing to the CPs and each other. Every I/O device has a command processor, so it can handle channel errors and integrated pcie errors in a way PCs cannot.
A PC with Chelsio NICs doing TCP offload with direct data placement or RDMA as well as Fiber Channel storage would be mini/mainframe-ish.
I think Naples is a very exciting development, because: - 1S/2S is obviously where the pie is. Few servers are 4S. - 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas - First x86 server platform with SHA1/2 acceleration - 128 PCIe lanes in a 1S system is unprecedented All in all Naples seems like a very interesting platform for throughput-intensive…
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Naples is based on Ryzen which, if you look at early benchmarks, is beating the competition on all fronts except gaming (suspectedly due to software optimisation and motherboard issues).
yes but four modules of ryzen to make this beastly naples chip isn't going to be clocked at the same frequencies. the top end intel chips have TDPs of 165W but 4 ryzen chips at 3.6ghz have a tdp of 65w a piece and you're not going to see a 260W server chip if you want to sell into the datacenter.
AMD might well steal some of the dual socket market with a dual socket, and maybe some of the quad socket market with dual sockets.
Considering that the current ryzen at $500 is relatively competitive with the $1,000 intel (basically a relabled Xeon with 4 memory busses in the LGA2011 server socket) a quad module (32 core/64 thread) in a socket sounds pretty good. Even if it's more watts than the intel.
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Is that because the workloads are fundamentally unsuitable for current GPU architectures or because no one has took a good stab at it yet? I know very little about computation genetics/biology but it sounds interesting.
FPGA type applications will probably pay way bigger dividends than GPU acceleration ever will. GPUs excel at problems where you can apply exactly the same logic to lots of data in parallel. CPUs can handle branching cases, where each operation requires a lot of decisions, a lot better. Sufficiently large FPGA chips could accelerate certain parts of the workflow, if not the whole thing, since they're extremely good at…
FPGAs run hot, don't have many transistors, limited clock rate, and are a pain to program.
So yeah a "Sufficiently large" chip, a "sufficiently fast clock", and a "sufficiently well written app" could theoretically do well. Problem is in the real world they aren't and developers aren't targeting them.
can anyone chime in as to why use PCIe over something more core to core direct? As I understand it, the CPU still needs to talk to a PCIe host/bridge controller. Why not have something that is more direct between processors?
So the single socket systems can have more pci-e lanes available, but the dual socket has less per socket because some of those lanes are used for hypertransport.
What I can't figure out is why Intel and AMD aren't using similar (Hypertransport for AMD and QPI for intel) to connect directly to GPUs in a cache coherent way. These days the faster interconnects spend a decent fraction of their latency just getting across the PCI-e bus twice.
So 100 Gbit networks, Infiniband, GPUs, etc all could take advantage of a lower latency cache coherent interface, but it's not available.
I suspect mainly because qpi and hypertransport are incompatible and pci-e is good enough for the high volume cases.
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The thermal design power is the maximum amount of heat generated by a computer chip or component that the cooling system in a computer is designed to dissipate in typical operation. TDP =/= power consumed
> TDP =/= power consumed Where do you think the heat comes from? Or where do you think the power that doesn't turn into heat goes?
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I did sequence-based bioinformatics back around 2006 or so. Very few of the operations used GPU. Things may have changed since I was working there, but the work at the time wasn't suited for a GPU architecture. Initial step was sequence cleanup, which is a hidden markov model executed over a collection of sequences of varying length, so hard to parallelize. Sequence annotation is embarassingly parallel on a per-libra…
"Lots of cores, lots of threads, and lots of main memory. That was the key." Very much this. Which is why I ended up theorycrafting that the AMD many core CPU's would be so useful.
Then a lot of code is very branchy but massively parallel leading to clusters of pure CPUs to be more flexible, which is important in research settings, and with higher utilization than mixed CPU/GPU clusters.
GPU code takes longer to get to market and has more specialized skills required then standard CPU orientated programming. Late to market means you miss a whole wave of experimental methods from the lab. i.e. GPU short read aligners came when long reads started to come out of the sequencing lab. Leading to people to stop doing short reads or at least stop doing pure short reads.
Secondly quite a bunch of the key staff at the large research institutes had been burned by previous hardware acceleration attempts and where not going to throw money at it until market proven.
Bio-informatics tends to cutting edge (the hemorrhaging kind) on the bio/lab tech side yet the production IT tends to balance that to doing the things we know as we already have enough risks. i.e. focus on the algorithms and robustness not on pure power.
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Why should it be dropped ? Isn't it just a hash function ?
Short story: because its role as a crypto hash function is sort of obsolete given that it's been proven to be broken, and faster, more secure alternatives exist. But for all practical purposes, SHA1 isn't about to disappear. MD5 has been shown to be broken since forever and people still write new code using it today.
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Pretty much all games are CPU intensive and it's not getting better. Try running on a cheap i3 from a few years ago and you'll understand your pain quickly.
Sorry but for years the mantra was for a gaming pic to invest in a i5 or even an i3 and spend the extra money in a good GPU. But for some bizarre reason suddenly everything that is not performing as an i7 7770k is a "bad cpu for gaming". It's ridiculous. Hell in 30 million households there are 8 jaguar x86 core gaming machines active now with an IPC that is probably (I assume) atrocious. I build my i7 4770 4 years ag…