Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

anandtech.com

Post reply on HN
Print view View original

1–10 of 169 posts

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#2

Post by throwawayish »

I think Naples is a very exciting development, because:

- 1S/2S is obviously where the pie is. Few servers are 4S.

- 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas

- First x86 server platform with SHA1/2 acceleration

- 128 PCIe lanes in a 1S system is unprecedented

All in all Naples seems like a very interesting platform for throughput-intensive applications. Overall it seems that Sun with it's Niagara-approach (massive number of threads, lots of I/O on-chip) was just a few years too early (and likely a few thousands / system to expensive ;)

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#4

Post by throwawayish »

kiddico wrote: post #3

Sorry, my google-fu isn't on point today; what's the difference between 1p and 1u. or 2p and 2u? My nomenclature knowledge is lacking ...

n-P / n-S / n-way = how many sockets/processors a system has. A 1S system has one socket / processor, a 2S system two, a 4S four and so on.

x U (or x HE, if you're talking with a German manufacturer, they like to make that mistake ... ;) are rack-units, i.e. how large the case is.

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#5

Post by sp332 »

kiddico wrote: post #3

Sorry, my google-fu isn't on point today; what's the difference between 1p and 1u. or 2p and 2u? My nomenclature knowledge is lacking ...

P = Processor and S = Socket (they're pretty interchangeable). U = rack Unit https://en.wikipedia.org/wiki/Rack_unit

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#7

Post by gigatexal »

throwawayish wrote: post #2

I think Naples is a very exciting development, because: - 1S/2S is obviously where the pie is. Few servers are 4S. - 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas - First x86 server platform with SHA1/2 acceleration - 128 PCIe lanes in a 1S system is unprecedented All in all Naples seems like a very interesting platform for throughput-intensive…

Let's hope this isn't niagra again: it needs to have decent clock speeds as IPC is still worth something today. But yes, I totally agree, this is an exciting chip.

Re: AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2

#8

Post by mtgx »

throwawayish wrote: post #2

I think Naples is a very exciting development, because: - 1S/2S is obviously where the pie is. Few servers are 4S. - 8 DDR4 channels per socket is twice the memory bandwidth of 2011, and still more than LGA-36712312whateverthenumberwas - First x86 server platform with SHA1/2 acceleration - 128 PCIe lanes in a 1S system is unprecedented All in all Naples seems like a very interesting platform for throughput-intensive…

Intel doesn't have SHA2 acceleration? ARMv8 has had it for like 2-3 years now...

And AMD should dump SHA1 acceleration in the next generation.

Post reply on HN