[deleted]
What happened to clockless computer chips?
21–30 of 49 posts
Re: What happened to clockless computer chips?
#22Chuck Moore's F18A Forth processor is async, and claims to execute a basic instruction in about 1.5ns, which is about 700k MIPS.
http://www.greenarraychips.com/home/documents/greg/PB003-110...
Re: What happened to clockless computer chips?
#23I asked an Intel chip designer about this and his opinion was that asynchronous processors are a "fantasy." His reasoning was that an asynchronous chip would still need to synchronize data communication within the chip. Apparently global clock synchronization accounts for about 20% of the power usage of a synchronous chip. In the asynchronous case, if you had to synchronize every communication, then the cost of communication is doubled.
Re: What happened to clockless computer chips?
#24I asked an Intel chip designer about this and his opinion was that asynchronous processors are a "fantasy." His reasoning was that an asynchronous chip would still need to synchronize data communication within the chip. Apparently global clock synchronization accounts for about 20% of the power usage of a synchronous chip. In the asynchronous case, if you had to synchronize every communication, then the cost of commu…
What do you mean by "synchronizing data communication within the chip"? For example, is there something that can be "synchronized" in a ring oscillator, the simplest kind of unclocked logic?
Re: What happened to clockless computer chips?
#25Earlier quoted context omitted.
I'm starting to feel like a broken record but... A perfect opportunity with risc-v.
Why do you say that? I can't see anything about RISC-V (or any ISA!) that makes a difference to those four points.
It's a very simple instruction set. Whatever the challenges are with asyc design and verification, the task will be simplified with a smaller/simpler processor design. The open source nature of it also means any company or researcher is free to do what they want with it. Design tool companies for example could create that alternative workflow for async and promote it by saying "look at the results we got on RISC-V" and make all the comparisons they want. They could also release the design if they wanted. It's hard to see any of that happening with something like ARM or x86.
Re: What happened to clockless computer chips?
#26Wave pipelining would be a more practical alternative to fully asynchronous design. It keeps the design synchronous (helps in simulation workflows) while removing the clock and pipeline registers for power and area reduction.
Re: What happened to clockless computer chips?
#27The quote from Ken Stevens, whose opinion I respect, makes a
compelling argument, and certainly Intel has a lot of expertise on
asynchronous design, but I'm wondering if its position is similar to
that of Kodak inventing digital imaging in the 1980s. That is, there
would be less money for Intel to make in a future where asynchronous
design prevails, so there's no incentive for them to develop it. With a
properly executed tool chain, asynchronous design would be a
comparable skill to software development (that is, less of an elitist
activity than it is now) and the circuits would be more likely to work
on the first try because a whole class of hardware bugs wouldn't be a
thing anymore. Any comments or am I just a plonker for believing this?
Re: What happened to clockless computer chips?
#28Earlier quoted context omitted.
Why do you say that? I can't see anything about RISC-V (or any ISA!) that makes a difference to those four points.
It's a very simple instruction set. Whatever the challenges are with asyc design and verification, the task will be simplified with a smaller/simpler processor design. The open source nature of it also means any company or researcher is free to do what they want with it. Design tool companies for example could create that alternative workflow for async and promote it by saying "look at the results we got on RISC-V" a…
Smaller ARM is quite simple, and as mentioned upthread there was already an async ARM - AMULET.
Tool complexity isn't really to do with size or complexity of design, although size affects runtime. It's a question of how accurate the physical modelling is and how well manufacturers trust an OK from the tools. And whether the engineers trust the tools and can use them effectively.
There aren't all that many design tool companies, too. Remember I worked for one. The Cadence/Synopsys duopoly is quite strong for the usual reasons.
Fundamentally what you're asking is for someone to make a quarter-million-dollar+ bet on async. It's easy to say "sure it'll be great" when it's not your money.
(Maybe the easy way to do it is to build an app for sending "yo!" to your friends, raise the $1.5m VC, and spend it on silicon instead...)
(Less snarky edit: you know that async isn't a magic dust to apply to existing designs, and that someone would have to write an entirely new core targeting RISC-V in an async style?)
Re: What happened to clockless computer chips?
#29"The answer is that although the chip ran three times as fast and used half the electrical power as clocked counterparts..." I thought another advantage was that it modularized chip design to some degree - ie you can improve individual sections to run much faster, without having to make the entire chip run at that speed - http://www.cs.virginia.edu/~robins/Computing_Without_Clocks.... In any case in a similar vein is…
Clock multipliers are already used to make individual sections run faster.
Re: What happened to clockless computer chips?
#30I asked an Intel chip designer about this and his opinion was that asynchronous processors are a "fantasy." His reasoning was that an asynchronous chip would still need to synchronize data communication within the chip. Apparently global clock synchronization accounts for about 20% of the power usage of a synchronous chip. In the asynchronous case, if you had to synchronize every communication, then the cost of commu…
What do you mean by "synchronizing data communication within the chip"? For example, is there something that can be "synchronized" in a ring oscillator, the simplest kind of unclocked logic?
I think this has been garbled, but he's referring to synchronisation across clock and power domains.
Normal D flip-flops require that, at the time of the clock edge arriving, the inputs are not changing. If you violate this you get "metastability" and data loss. Special structures are needed when you move data from a fast-clocked area to a slower. On processors, usually the core is at one (maybe variable!) speed while the peripherals and DRAM are at a lower speed (what used to be called "front side bus").
As to the application for async, maybe he's right and maybe he isn't. There would have to be synchronisation to fixed external bus speeds, but 20% seems very high as a proportion of power consumption.