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Intel Shows 2.5D FPGA at ISSCC

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Re: Intel Shows 2.5D FPGA at ISSCC

#101

Post by mrb »

pjc50 wrote: post #93

I'm slightly confused why everyone's talking about CPUs and ignoring the FPGA! Anyway, it's an interesting technique. An extension of chip-on-module packaging where instead of having a circuit board made of FR4 you have a tiny PCB made of multilayer silicon. This allows fast connections between chips made with different processes (CPU/DRAM/Flash are somewhat incompatible), and joining small chips together into large…

The HN headline was changed by a moderator, I suppose to comply with the guideline that the submitted headline should match the article's title.

I originally submitted it with a headline describing the 14nm AMD Zen core being 10% smaller than the 14nm Intel current-gen core (and I accidentally linked to page 1 of the article instead of page 2.)

Re: Intel Shows 2.5D FPGA at ISSCC

#102

Post by jcoffland »

m_mueller wrote: post #28
jcoffland wrote: post #27

Earlier quoted context omitted.

Have you looked into Xeon Phi? They have up to 288 threads. With a 256 thread Xeon we got good speed ups using up to 128 threads with Folding@home's latest GROMACS core (0xa7). With higher thread counts it failed to improve. In the long-run massively parallel CPUs could outpace GPUs precisely because of their flexibility. Note that the 0xa7 core also uses 256 AVX. That's multiple CPU threads and vector instructions.

I haven't tried MICs personally, but AFAIK you need vectorization to match current Pascal generation GPU performance with Knight's landing -> which is where my comment applies. I don't doubt that you can get good speedups when this applies to your code already, but if you start from naive CPU code you'll have a lot of work to do, which IMO is similar to the work needed to port to GPGPU.

That is true. CPUs are catching up to GPUs in some ways. Intel is doing its best to take this market from NVidia. The future will tell.

Re: Intel Shows 2.5D FPGA at ISSCC

#103

Post by i80and »

lightedman wrote: post #88
oliwarner wrote: post #43

Getting a bit bored of leaks, press releases and even specs. The proof of a CPU is in how it benchmarks across real workloads. We're 2-3 weeks away from global release. People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts. But instead of any firm performance figures, we have rumour. The only reason I can imagine AMD is still keeping the press und…

"The proof of a CPU is in how it benchmarks across real workloads." Define 'real workload' here. Are we talking about a workload where the compiler specifically optimizes for Intel, or where the executable chooses unoptimized paths if it finds anything other than intel processors inside? Because I've found that when it comes to raw x86, no SSE anything or other nonsense; pure, unadulterated original x86, AMD simply o…

"Unadulterated original x86" doesn't really exist, and hasn't mattered for decades at least.

Do you mean the 8086's instruction set? Many of those instructions are now implemented in microcode; sure, you can use them, but they're going to be dog slow. Turns out, nobody uses them.

Do you mean the i586 instruction set? Your system calls are going to be slow, since you have to trigger an interrupt.

Do you just mean 32-bit x86? That covers a large set of incompatible extensions among different vendors, and is of rapidly decreasing relevancy.

Do you just mean scaler instructions? That's really just hamstringing yourself: a lot of performance-sensitive applications involve manipulating vectors, and SIMD is a fairly easy and effective win.

Re: Intel Shows 2.5D FPGA at ISSCC

#104

Post by pjc50 »

matt_wulfeck wrote: post #99
pjc50 wrote: post #93

I'm slightly confused why everyone's talking about CPUs and ignoring the FPGA! Anyway, it's an interesting technique. An extension of chip-on-module packaging where instead of having a circuit board made of FR4 you have a tiny PCB made of multilayer silicon. This allows fast connections between chips made with different processes (CPU/DRAM/Flash are somewhat incompatible), and joining small chips together into large…

Can you ELI5 how putting an FPGA on a cisc die will ultimately improve performance? Does it affect both multi core and single core benchmarks?

It doesn't, there are two unrelated announcements in a separate article!

The use of multi-die technology lets Intel build transcievers that run at a higher speed than the main die - 28GHz SERDES on a 1GHz FPGA.

Re: Intel Shows 2.5D FPGA at ISSCC

#105

Post by smueller1234 »

DannyBee wrote: post #73
oliwarner wrote: post #43

Getting a bit bored of leaks, press releases and even specs. The proof of a CPU is in how it benchmarks across real workloads. We're 2-3 weeks away from global release. People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts. But instead of any firm performance figures, we have rumour. The only reason I can imagine AMD is still keeping the press und…

"People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts." Err, for the people that matter, they probably are. I'm not sure why you would think otherwise. Certainly you realize their large purchasers vastly dwarf people frequenting tech sites. They 100% have done benchmarking/testing with, say, their top N chip purchasers, well before now, and alrea…

Nitpick: I'd like to point out that there's significant overlap between the two groups. To wit, I read hardware sites (from the realworldtech forum to anandtech and friends) and I've made 8 digit server hardware investment choices for work. This being said, the actual product focus between a typical core i7...K review and the mid range Xeons we've been purchasing are obviously not the same despite the similarity in architecture. We do get to do our own benchmarking, though. ;)

Re: Intel Shows 2.5D FPGA at ISSCC

#106

Post by [deleted] »

DannyBee wrote: post #73
oliwarner wrote: post #43

Getting a bit bored of leaks, press releases and even specs. The proof of a CPU is in how it benchmarks across real workloads. We're 2-3 weeks away from global release. People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts. But instead of any firm performance figures, we have rumour. The only reason I can imagine AMD is still keeping the press und…

"People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts." Err, for the people that matter, they probably are. I'm not sure why you would think otherwise. Certainly you realize their large purchasers vastly dwarf people frequenting tech sites. They 100% have done benchmarking/testing with, say, their top N chip purchasers, well before now, and alrea…

[deleted]

Re: Intel Shows 2.5D FPGA at ISSCC

#107

Post by [deleted] »

DannyBee wrote: post #73
oliwarner wrote: post #43

Getting a bit bored of leaks, press releases and even specs. The proof of a CPU is in how it benchmarks across real workloads. We're 2-3 weeks away from global release. People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts. But instead of any firm performance figures, we have rumour. The only reason I can imagine AMD is still keeping the press und…

"People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts." Err, for the people that matter, they probably are. I'm not sure why you would think otherwise. Certainly you realize their large purchasers vastly dwarf people frequenting tech sites. They 100% have done benchmarking/testing with, say, their top N chip purchasers, well before now, and alrea…

[deleted]

Re: Intel Shows 2.5D FPGA at ISSCC

#108

Post by gpderetta »

kogepathic wrote: post #55
mrb wrote: post #3

I should have linked to the second page: http://www.eetimes.com/document.asp?doc_id=1331317&page_numb... Relevant quote: "AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor. Analysts and even Intel engineers in the session said the Zen core is clearly competitive though many confidential variables will determine whether the die a…

> AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor. We need to compare apples to apples. AMD's Zen chips have no IGP, while most Intel chips are shipping with an Intel GPU. If you look at an Intel die shot, about half of the area is taken by the GPU. [0] Since the current batch of Zen SKUs lacks any IGP, I'd be worried if they…

I haven't read the article (I know...), but AMD is specifically talking about the 'core' part of the microprocessor (there are 4 or 8 of them on a Ryzen CPU) . The core includes the L2 cache (as it is part of the core per se), but not L3, IGP and other uncore parts.

Re: Intel Shows 2.5D FPGA at ISSCC

#109

Post by oliwarner »

lightedman wrote: post #88
oliwarner wrote: post #43

Getting a bit bored of leaks, press releases and even specs. The proof of a CPU is in how it benchmarks across real workloads. We're 2-3 weeks away from global release. People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts. But instead of any firm performance figures, we have rumour. The only reason I can imagine AMD is still keeping the press und…

"The proof of a CPU is in how it benchmarks across real workloads." Define 'real workload' here. Are we talking about a workload where the compiler specifically optimizes for Intel, or where the executable chooses unoptimized paths if it finds anything other than intel processors inside? Because I've found that when it comes to raw x86, no SSE anything or other nonsense; pure, unadulterated original x86, AMD simply o…

Other nonsense? These additional instruction sets aren't just a gimmick, they exist to do more work faster.

But my definition of two workload really just means a spectrum of different sorts of computation so we can see how various subsystems compare.

Re: Intel Shows 2.5D FPGA at ISSCC

#110

Post by gpderetta »

RandomOpinion wrote: post #100
mtgx wrote: post #64

Earlier quoted context omitted.

It's actually super-relevant. Here's what this means. Intel has about 10% advantage in process technology. Yet despite that, AMD's chip is still 10% smaller than Intel's chip. That gives AMD an effective 20% architectural advantage over Intel for similar performance. This is why Intel is now scrambling to "streamline" its architecture as soon as possible (but won't be able to do it for the next 3 years or so). A smal…

> Here's what this means. Intel has about 10% advantage in process technology. Yet despite that, AMD's chip is still 10% smaller than Intel's chip. That gives AMD an effective 20% architectural advantage over Intel for similar performance. No, the conclusion you should be drawing is "AMD is using ~20% less transistors per core. What did AMD not implement that Intel did and how badly does that hurt Ryzen's performance…

Apparently two full 256 bit ALUs capable of 4 cycle MAD and 14 cycle division. Those probably take a lot of space.

It is probably a good call on AMD part though, as applications that are sensitive to AVX performance are still rare and if they can get a cheaper core which is faster on integer loads it is a good tradeoff.

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