Working on a pcie card, not 100gbps but hopefully not $10k also: https://github.com/theocean154/fpga-board
Liberouter Combo Cards – FPGA boards focused on network data processing
11–20 of 36 posts
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#12I saw the page via wayback machine since the site was down at the time. Seems like a cool academic project. I've been getting into FPGAs personally, with this exact application in mind. I've been really stymied by how to process packets in hardware. The obvious approach seems to be to run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it. But is there a better way? How much performance would one…
Regarding PCIe - assuming you're using a hard IP MAC/PHY in your fpga, it's a packed-based protocol that basically only has three packets - read requests, write requests and completions. Requests have an address and a length, and target physical memory. Completions have the data and a matching tag from the read request. A dma transaction is just when the endpoint generates the request instead of the host CPU, but otherwise it's basically identical.
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#13I saw the page via wayback machine since the site was down at the time. Seems like a cool academic project. I've been getting into FPGAs personally, with this exact application in mind. I've been really stymied by how to process packets in hardware. The obvious approach seems to be to run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it. But is there a better way? How much performance would one…
Generally speaking, FPGAs are for building hardware pipelines with fixed throughput and finite state machines to control things. If your first thought is "Linux", you're almost certainly better off with an off the shelf SoC. If you have a well understood problem (say, filtering packets based on a handful of patterns), you would design a filtering pipeline that would connect between two Ethernet MACs, applying the fil…
The "connecting two ethernet MACs [with] filtering" seems like an interesting project. I guess a "simple" (and possibly useless) idea could be to do filtering based on MAC addresses in the enthernet frame. Is there open IP for this? I guess I'm asking how a hobbyist gets into this :-) If anyone knows of an existing project, I'd appreciate a pointer.
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#14I saw the page via wayback machine since the site was down at the time. Seems like a cool academic project. I've been getting into FPGAs personally, with this exact application in mind. I've been really stymied by how to process packets in hardware. The obvious approach seems to be to run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it. But is there a better way? How much performance would one…
Dont be fooled by the appearance of VHDL/Verilog. you are building hardware with them. So writing a TCP/IP stack in VHDL would be almost like physically building a TCP/IP stack with physical logic gate IC's.
I looked into this a few years ago. If you can settle for just sending bytes on an ethernet cable, you can relatively easily TX/RX using UDP Multicast. The FPGA can beam bits straight to the PHY adapter and out they go.
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#15I saw the page via wayback machine since the site was down at the time. Seems like a cool academic project. I've been getting into FPGAs personally, with this exact application in mind. I've been really stymied by how to process packets in hardware. The obvious approach seems to be to run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it. But is there a better way? How much performance would one…
> run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it
Letting the OS touch more than a small percentage of the packets would be a gross waste of resources. If you want to write a program to process packets, use a real processor. (Putting an FPGA in a computer and then running a soft core on the FPGA is even sillier for performance.)
The main reason to use an FPGA for this is to build structures that effectively encode your firewall or other layer processing rules in tables in the hardware, so the hardware can make a decision without having to consult the processor. MPLS and VLAN routing is the obvious case, but you can usually keep a short IP routing table in there too. Ideally you'd be able to make this decision early on while recieving a packet so you can start transmitting it while the last bits are still coming in. What you want to avoid is buffering ("bufferbloat").
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#16I saw the page via wayback machine since the site was down at the time. Seems like a cool academic project. I've been getting into FPGAs personally, with this exact application in mind. I've been really stymied by how to process packets in hardware. The obvious approach seems to be to run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it. But is there a better way? How much performance would one…
> run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it Letting the OS touch more than a small percentage of the packets would be a gross waste of resources. If you want to write a program to process packets, use a real processor. (Putting an FPGA in a computer and then running a soft core on the FPGA is even sillier for performance.) The main reason to use an FPGA for this is to build structure…
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Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#17Earlier quoted context omitted.
Generally speaking, FPGAs are for building hardware pipelines with fixed throughput and finite state machines to control things. If your first thought is "Linux", you're almost certainly better off with an off the shelf SoC. If you have a well understood problem (say, filtering packets based on a handful of patterns), you would design a filtering pipeline that would connect between two Ethernet MACs, applying the fil…
The "connecting two ethernet MACs [with] filtering" seems like an interesting project. I guess a "simple" (and possibly useless) idea could be to do filtering based on MAC addresses in the enthernet frame. Is there open IP for this? I guess I'm asking how a hobbyist gets into this :-) If anyone knows of an existing project, I'd appreciate a pointer.
OpenCores is one possible source of examples. You could start by modifying e.g. http://opencores.org/project,mac_layer_switch
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#18Earlier quoted context omitted.
Generally speaking, FPGAs are for building hardware pipelines with fixed throughput and finite state machines to control things. If your first thought is "Linux", you're almost certainly better off with an off the shelf SoC. If you have a well understood problem (say, filtering packets based on a handful of patterns), you would design a filtering pipeline that would connect between two Ethernet MACs, applying the fil…
The "connecting two ethernet MACs [with] filtering" seems like an interesting project. I guess a "simple" (and possibly useless) idea could be to do filtering based on MAC addresses in the enthernet frame. Is there open IP for this? I guess I'm asking how a hobbyist gets into this :-) If anyone knows of an existing project, I'd appreciate a pointer.
It is definitely possible, me and a few other students did it in a university course. Assuming the FPGA at least has a media access controller (translates bits to analogue signals) it is not to hard to encode/decode ethernet frames.
Sadly, on the top of my head I do not know of any open IP.
We wrote our own, but it is closed.
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#19I saw the page via wayback machine since the site was down at the time. Seems like a cool academic project. I've been getting into FPGAs personally, with this exact application in mind. I've been really stymied by how to process packets in hardware. The obvious approach seems to be to run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it. But is there a better way? How much performance would one…
> run an RTOS or even full-fledged linux if your FPGA has hard IP cores on it Letting the OS touch more than a small percentage of the packets would be a gross waste of resources. If you want to write a program to process packets, use a real processor. (Putting an FPGA in a computer and then running a soft core on the FPGA is even sillier for performance.) The main reason to use an FPGA for this is to build structure…
> What you want to avoid is buffering ("bufferbloat").
Excess buffering is a problem, but a little bit is fine unless you're trying to do high frequency trading. If you don't move packets to an external DRAM, you're in no danger of having bloated buffers with just the memory on the FPGA.
Or you could implement an active queue management algorithm to keep your buffers from inducing too much unnecessary latency even when they are generously sized. There are a bunch of AQMs out there to pick from, of varying complexity. And it doesn't seem like there's near enough research into hardware implementations suitable for use in switches or network co-processors.
Re: Liberouter Combo Cards – FPGA boards focused on network data processing
#20Earlier quoted context omitted.
Generally speaking, FPGAs are for building hardware pipelines with fixed throughput and finite state machines to control things. If your first thought is "Linux", you're almost certainly better off with an off the shelf SoC. If you have a well understood problem (say, filtering packets based on a handful of patterns), you would design a filtering pipeline that would connect between two Ethernet MACs, applying the fil…
The "connecting two ethernet MACs [with] filtering" seems like an interesting project. I guess a "simple" (and possibly useless) idea could be to do filtering based on MAC addresses in the enthernet frame. Is there open IP for this? I guess I'm asking how a hobbyist gets into this :-) If anyone knows of an existing project, I'd appreciate a pointer.
I don't know about open IP, but it would be fairly straightforward but not trivial. Knowing verilog would be required, though, but it can be learned from a digital design book [1]. From there, you would probably want some experience in using the tools. For example, for Xilinx FPGAs, you could run through the Vivado tutorials. Then to design the IP you would design the state machines and logic to take data from one ethernet controller (for example, the Xilinx ethernet MAC [2]) and send it to another. The actual verilog would not be especially complex, however interfacing with the ethernet controllers and other peripherals would take some time.
[1] Such as https://www.amazon.com/Logic-Design-Verification-SystemVeril... [2] https://www.xilinx.com/support/documentation/ip_documentatio...