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HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

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Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#71
post #70
post #54

Two points: a short question and a longer theory about why only 16KB. The question: how viable is an open-source, publicly-auditable secure boot implementation? Not TPM theater or whatever, but a hardened hardware configuration that could be used to implement truly verifiable boot. (If anyone from RISC-V is reading this, I think there is a very noteworthy amount of money in building a truly securely bootable referenc…

The whole of your second point is ridiculous conspiracy theory. It is perfectly reasonable to do enough formal verification to ensure that your chip works first time. Linux is not going to "stress" your chip more. And nobody deliberately cuts out a viable market sector unless they've got another product to put in it. On-chip SRAM is just expensive in terms of area. It's comparable to what you get on Cortex-M devices.…

> The whole of your second point is ridiculous conspiracy theory.

Theory, yes. Conspiracy theory, emphatically not, sorry for the misunderstanding. I have no ill will towards the RISC-V ISA and no disagreement with SiFive's operations. Like others here I was just trying to figure out the huge disparity between the CPU clock speed and the onboard memory, in my case with sorely insufficient understanding of the field.

> It is perfectly reasonable to do enough formal verification to ensure that your chip works first time.

Oh, okay then. That's really amazing, I didn't know that :)

> Linux is not going to "stress" your chip more.

Like I said, I'm a bit ignorant here. I was just thinking along the lines of how eg an i7 with faulty L2 cache could be re-designated as an i5, but in this case they're not sure what's faulty, etc.

There's also the fact that CPUs do have errata... (?)

> And nobody deliberately cuts out a viable market sector unless they've got another product to put in it.

Absolutely! What I was saying was that I theorize that this is a first-run design and that another chip was going to follow up. I'm increasingly confident I'm wrong about exactly why (eg, now I understand about the RAM problem)

> On-chip SRAM is just expensive in terms of area. It's comparable to what you get on Cortex-M devices. There are no chips with enough onboard SRAM to run Linux. You can't really run Linux without an external DRAM interface, and then you have to find somewhere to put the DRAM.

I see. Mmm :/

> People keep forgetting about this on the Pi because the DRAM is stuck on top of the SoC package.

Has a look at a picture oh wow so it is, that's amazing.

> Sure, maybe if this is a success they'll pay the licensing fees for a DDR3 interface + MMU, or write one themselves.

Hopefully this run is an incentivisation to get some support for that!

> I think you'd also want at least 600MHz for Linux, 320 is kind of slow these days.

Hmm, that's quite true, yeah. (It's kind of sad how speed-hungry the kernel is nowadays - I have a 32MHz PDA with an OS (EPOC, precursor of Symbian) that draws draggable windows on a little monochrome touchscreen LCD, I can fling the windows around faster than the crystals can update :D)

I would absolutely buy a 320MHz Linux device with an open-source secure boot story though. Text communication doesn't need a snappy CPU.

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#72
post #62
post #54

Two points: a short question and a longer theory about why only 16KB. The question: how viable is an open-source, publicly-auditable secure boot implementation? Not TPM theater or whatever, but a hardened hardware configuration that could be used to implement truly verifiable boot. (If anyone from RISC-V is reading this, I think there is a very noteworthy amount of money in building a truly securely bootable referenc…

SiFive is working on two chips. This one is basically an atmel competitor. They are also working on a workstation class many core chip.

Oh, I see. That makes sense.

I'm definitely looking forward to seeing the many-core design!

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#73
post #54

Two points: a short question and a longer theory about why only 16KB. The question: how viable is an open-source, publicly-auditable secure boot implementation? Not TPM theater or whatever, but a hardened hardware configuration that could be used to implement truly verifiable boot. (If anyone from RISC-V is reading this, I think there is a very noteworthy amount of money in building a truly securely bootable referenc…

> how viable is an open-source, publicly-auditable secure boot implementation?

Depends if you trust your fab. I suppose you can take random samples and decap them at considerable expense, but then the public has to trust the auditor.

> I think there is a very noteworthy amount of money in building a truly securely bootable reference design.

I disagree. I think there are two critical problems with this: firstly, getting the community to agree on what they consider "truly secure", and secondly getting enough people to buy a system that is (necessarily due to small production runs) slower and more expensive than comparable Intel or even ARM.

If you're willing to trust a manufacturer you can buy secure-bootable ARM devices today with OTP key regions that boot Linux (e.g. iMX). So the market for the proposed "open" system is only people who are willing to trust you but are paranoid enough to not trust one of the existing manufacturers.

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#74
post #66

Earlier quoted context omitted.

Or you can solve it as done in GRLIB (www.gaisler.com/index.php/downloads/leongrlib), with having all on-chip peripheral information (memory & irq map, etc) specified in a ROM configuration area (which is automatically generated at synthesis time).

or we could continue using device trees, which are much more expressive and were actually designed for this purpose.

Device trees needs to be written to match the hardware, compiled and supplied to the kernel. So not really as nice as "boot this kernel on any hardware".

Device trees are needed because manufacturers did not create self describing hardware.

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#75
post #73
post #54

Two points: a short question and a longer theory about why only 16KB. The question: how viable is an open-source, publicly-auditable secure boot implementation? Not TPM theater or whatever, but a hardened hardware configuration that could be used to implement truly verifiable boot. (If anyone from RISC-V is reading this, I think there is a very noteworthy amount of money in building a truly securely bootable referenc…

> how viable is an open-source, publicly-auditable secure boot implementation? Depends if you trust your fab. I suppose you can take random samples and decap them at considerable expense, but then the public has to trust the auditor. > I think there is a very noteworthy amount of money in building a truly securely bootable reference design. I disagree. I think there are two critical problems with this: firstly, getti…

All these points are very true; chains like these are unfortunately based on a root of implicit trust.

I make some counter-arguments:

Secure boot forms the trust basis that the device is definitively running the code you put on it without modification, so is arguably the most security-sensitive aspect of the system, in some ways more critically so than the kernel, network-facing daemons, etc. It is at least as important as those components.

I'm confident a publicly-auditable open-source secure boot implementation would attract fairly reasonable academic interest from the security field and be hacked on (from theoretical design down to implementational edge cases) by the community until it was very very good.

That would help avoid this sort of thing - http://www.cnx-software.com/2016/10/06/hacking-arm-trustzone... - which is currently only an issue because vendor engineering teams are not perfect and there's no widespread collaboration. (There is, of course, also the likely truth that there are similar "vulnerabilities" in all commercial secure boot implementations. Think TSA007.)

The one issue I will acknowledge is that if such a reference design existed and was widely implemented, it would be a very good question as to which manufacturers had "accidents" in the manufacturing process near the secure-boot areas of the chips.

If I understand correctly, the other very major issue (which is kind of really ironic considering what I've just said) is that you have to sign NDAs to understand how the implementation works, and AFAIK even to just use it. So I (a random tinkerer) can't configure a "really trustworthily secure" Linux system, only a major manufacturer/system integrator/etc can. I understand this situation but from the standpoint of paranoid individual security it's crazy - security by obscurity, anyone?

If it is possible for me to play with OTP on iMX from a hobbyist perspective without shelling out for some NDA'd SDK, I'm tentatively interested for what it's worth.

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#76
post #65
post #40

Earlier quoted context omitted.

Depends what you mean by "enough". 24MHz is "enough" for 20 bits@96kHz ADC and some post processing. But 20 bits@96kHz is not decent. For reasonable SNR, you need at least 24 bits, and even then "the experts" offload to an external CPU http://www.tested.com/tech/pcs/454839-tested-why-high-end-pc... For signal (less audio are more "controller") with high precision you need micro controllers with the power of at least…

Most sensible people stick to 16 bits @ 48kHz, especially if it's not a pro-audio device but just something with a MEMS mic and 8ohm speaker.

And they would be interested in signal processing a 50kHz LF radio transmission why?

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#77
post #75
post #73

Earlier quoted context omitted.

> how viable is an open-source, publicly-auditable secure boot implementation? Depends if you trust your fab. I suppose you can take random samples and decap them at considerable expense, but then the public has to trust the auditor. > I think there is a very noteworthy amount of money in building a truly securely bootable reference design. I disagree. I think there are two critical problems with this: firstly, getti…

All these points are very true; chains like these are unfortunately based on a root of implicit trust. I make some counter-arguments: Secure boot forms the trust basis that the device is definitively running the code you put on it without modification, so is arguably the most security-sensitive aspect of the system, in some ways more critically so than the kernel, network-facing daemons, etc. It is at least as import…

imx53 is sort of possible to play with: https://cache.freescale.com/files/32bit/doc/ref_manual/iMX53...

Boot documentation is chapter 7. References "high assurance boot" functionality in the onboard boot ROM, but doesn't give out docs for the ROM. On the other hand, it's not a large ROM so you could just dump and reverse-engineer it.

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#78

320 MHz core clock is very impressive, compare to <= 200 MHz typical of Cortex-M3/4 impls. However at this freq, flash (instruction) readout becomes the bottleneck. While Cortex-M chips typically include some on-chip flash acceleration, this chip instead went for external flash + I-Cache. The new Cortex-M7 chip STM32F7 has both flash accel and I-Cache. It remains to be seen whether this chip can sustain real-world wo…

Modern non-volatile RAM technologies (like XPoint) would be perfect for chips like this. Much faster than flash and usable as RAM.

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#79
post #71
post #70

Earlier quoted context omitted.

The whole of your second point is ridiculous conspiracy theory. It is perfectly reasonable to do enough formal verification to ensure that your chip works first time. Linux is not going to "stress" your chip more. And nobody deliberately cuts out a viable market sector unless they've got another product to put in it. On-chip SRAM is just expensive in terms of area. It's comparable to what you get on Cortex-M devices.…

> The whole of your second point is ridiculous conspiracy theory. Theory, yes. Conspiracy theory, emphatically not, sorry for the misunderstanding. I have no ill will towards the RISC-V ISA and no disagreement with SiFive's operations. Like others here I was just trying to figure out the huge disparity between the CPU clock speed and the onboard memory, in my case with sorely insufficient understanding of the field.…

> huge disparity between the CPU clock speed and the onboard memory

I think that's RISC "working as intended"; the tradeoff was always supposed to be that you got to issue lots of simple instructions at high speed. I can't find what manufacturing process they're using (?nanometers) but it sounds like it's simply a "why not?" outcome of the design process that the chip is very fast. It doesn't have all that many peripherals either, by modern standards.

Edit: the answer is here - https://news.ycombinator.com/item?id=13067833 - other chips that have onboard Flash are necessarily slower. This doesn't, so it can be faster.

SRAM just takes up a lot of space. Hard to tell without gate counts or die shots but the 16k+16k could easily be over half the die.

EPOC is one of those extraordinary things that can be called a great technological achievement with a tiny dedicated fandom that nonetheless became a dead-end. Like Amiga, Concorde, BBC Domesday Project, etc. I do wish we could have snappier GUIs on our ten-times-faster systems.

Re: HiFive1: A RISC-V-based, Open-Source, Arduino-Compatible Development Kit

#80
post #33

I looked over the Chisel source code and the barebones datasheet [1]. This chip has a couple of unique features: 1. It doesn't have any onboard NVRAM (same limitation as the open-v). However, it does have a directly memory mapped quad-SPI peripheral and icache, which is a great alternative and might be better for applications that require a large amount of data. Note that an icache would still be required even if it…

I'm worried this leads to the zoo of random hardware that we see on ARM, which makes supporting Linux distros on ARM such a PITA. It would be better if the basic hardware — serial ports and such — was in a standard location for all RISC-V machines, and all the rest of the hardware was discoverable at runtime (like PCs, mostly).

The parent comment has proven oddly controversial going down to 0 and up to +5 and back down again. So let me try to do better and clarify what I mean. For context, I am maintaining Fedora on RISC-V: https://fedoraproject.org/wiki/Architectures/RISC-V .

On a PC, there is a serial port at a standard location. It's not "discoverable", but every PC you care about has one at the same address, and it's incredibly easy to use with a tiny bit of assembler. You can always print messages, even in the earliest parts of early boot.

On non-PC platforms (I've used ARMv7, ARMv8, POWER) there's a zoo of serial ports. There are at least a half dozen different bits of hardware, on different ports, self-describing, not discoverable at all, or mentioned in device tree in multiple different ways. Some even require PCI so needing ugly hacks to output early boot messages.

Critically, if you get the wrong serial port, you cannot see any boot messages at all. There's no way to tell what's going wrong.

So I think, for serial ports, the PC approach is definitely, clearly better.

For other hardware, it should just be self-describing. PCI and USB are the model examples here. And in fact, why not just use those?

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