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X86 Register Encoding

eklitzke.org

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Re: X86 Register Encoding

#51

Post by TheDauthi »

kr7 wrote: post #50
Flow wrote: post #43

Earlier quoted context omitted.

Interesting, would you mind sharing the script or give a short overview how it works?

Here it is (warning: Perl): http://pastebin.com/MFmDzY0g It calls "objdump -d" on the binary, which is binutil's disassembler. objdump prints each instruction out in the following format: 5dc: 67 80 7d 00 00 cmpb $0x0,0x0(%ebp) The first part is the instruction offset; the second is the bytes that comprise the instruction; the third part is the instruction in AT&T assembly syntax. The script uses regexs to cut off th…

Might I suggest http://pastebin.com/2PHXi78A instead? It handles a few bugs from the original, and cleans the nested loops.

Re: X86 Register Encoding

#52

Post by gens »

eloff wrote: post #49
gens wrote: post #45

Earlier quoted context omitted.

Amd64 encoding, as is the case with most x86 encodings, is longer then it should be. Due to the two companies not communicating/cooperating. That is the one advantage that i think ARM has over x86/amd64. That ARM encoding is much shorter.

You just repeated your point without adding anything new, that doesn't help your argument.

They couldn't use the shorter code space. So no, they could not do whatever they wanted. (note that making a completely new instruction encoding scheme would fail for obvious reasons)

Re: X86 Register Encoding

#53

Post by eloff »

gens wrote: post #52
eloff wrote: post #49

Earlier quoted context omitted.

You just repeated your point without adding anything new, that doesn't help your argument.

They couldn't use the shorter code space. So no, they could not do whatever they wanted. (note that making a completely new instruction encoding scheme would fail for obvious reasons)

I disagree, 64bit mode did not have to have any kind of instruction compatibility. It could have been a completely new instruction encoding scheme. A 64bit process must run all 64bit code, there is no invoking 32bit code from a 64bit process on any modern OS for AMD64.

Re: X86 Register Encoding

#54

Post by ant6n »

eloff wrote: post #53
gens wrote: post #52

Earlier quoted context omitted.

They couldn't use the shorter code space. So no, they could not do whatever they wanted. (note that making a completely new instruction encoding scheme would fail for obvious reasons)

I disagree, 64bit mode did not have to have any kind of instruction compatibility. It could have been a completely new instruction encoding scheme. A 64bit process must run all 64bit code, there is no invoking 32bit code from a 64bit process on any modern OS for AMD64.

And adding to that, they could've probably come up with some sort of 32bit per instruction risc structure where the the makeup overlaps with the cisc x86 encoding. For example, pack the 16 bits of a normal x86 instruction into the first bits of the risc, then add second source register and a bit or to each operand to increase the number of registers.
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