Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

anandtech.com

Post reply on HN
Print view View original

41–50 of 59 posts

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#41

Post by nickpsecurity »

mjevans wrote: post #34
trendia wrote: post #19

Earlier quoted context omitted.

AMD wants to gain market share. The way to do that is to develop technology that competes with existing market leaders. If Intel were involved, then AMD would gain no strategic advantage.

I would argue that in some respects they would have //less// of a strategic advantage, but that consumers would see the most benefit from everyone getting along and competing on merit on an open playing field. Even in the latter case AMD would still have /an/ advantage as they would at least still be in the primary game, and would also be restricting Intel to targeting that same hardware interface.

That's a good point. They did that with 64-bit x86 IIRC.

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#42

Post by honkhonkpants »

wmf wrote: post #37
honkhonkpants wrote: post #28

Given AMD's involvement, what is the difference between this and coherent hypertransport?

The difference is that NVIDIA, Mellanox, and Xilinx never adopted coherent Hypertransport.

There was at one point cHT IP available for Xilinx. But that is what I am kinda getting at. Did cHT fail for reasons of pure timing? Too far ahead of the market?

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#44

Post by sargun »

codebook wrote: post #35
iheartmemcache wrote: post #29

Earlier quoted context omitted.

Xilinx offers 25gbps single-lanes that can bond up to 4x to get IEEE 802.3-2012 spec compliance for free* with their suite. Sure, you're going to need to control those trace impedences and your board won't be something coming out of OSH Park, but those are definitely attainable speeds for the consumer (e.g., in the single-thousands of dollars; not 800k Cisco VXR tier-1 infrastructure). You can configure it in CAUI-10…

Thanks for the info. I would like to search the term and understand how they can achieve 200ns latency. Maybe am I the only one who thinks 200ns latency as completion latency?

It sounds like 200ns is the upper expected network delay. If 9 network delays at 200ns are experienced, it'll retrain the link.

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#45

Post by valarauca1 »

I really enjoy the way AMD and Nvidia fight.

Nvidia makes GSync. So the GPU can control and adjust display refresh rate on the fly. Proprietary, closed source, requires private Nvidia License. AMD makes FreeSync. FreeSync open sourced, added to the HDMI, and Display Port standards.

Now we see Nvidia makes NvLink. Proprietary, very fast, requires private Nvidia license. AMD partners with IBM, Google, etc., etc. to make OpenCAPI an open standard that can revise/replace PCIe3.0

Why does this feel like Microsoft vs Linux but with Hardware Standards.

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#46

Post by gpderetta »

convolvatron wrote: post #30
visionscaper wrote: post #24

Hmmm, interesting. I wonder what this means for the new Intel Xeon Phi Knights Landing? I liked the approach of many cores on one bootable chip, all having a reasonable amount of local memory, and high bandwidth interconnects: no need to offload data to a peripheral (GPU) device. However with this standard the currently limited bandwidth between peripherals and the main cpu will improve a lot. To me it is obvious why…

well, i think its a bit more about market segments and interoperability than anything else. currently overall systems from ibm, and, and intel are fundamentally incompatible. the PCI-E bus that knights landing hangs off of is a qualitatively different thing than the kinds of memory-coherent inter-cpu busses that are being addressed with the CAPI proposal. Intel has their own proprietary QPI. AMD has a quasi-open hype…

There are KNL variants that sit on a cpu socket and talk to the rest of the system via QPI.

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#47

Post by mablap »

bch wrote: post #18

It felt so buried in the article, it's worth pointing out: OpenCAPI == "Open Coherent Accelerator Processor Interface"

This is what I was looking for before deciding to read the article or not. Didn't find it, came back here, and now I just won't bother. Unfortunate.

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#49

Post by cmrx64 »

appleflaxen wrote: post #48
bch wrote: post #18

It felt so buried in the article, it's worth pointing out: OpenCAPI == "Open Coherent Accelerator Processor Interface"

Thanks for posting this. What does "coherent" mean in this context, and why is it special?

Basically, https://en.wikipedia.org/wiki/Cache_coherence. You want to ensure all the devices on the bus have the same view of memory contents.

Re: OpenCAPI Unveiled: AMD, IBM, Google, Xilinx, Micron and Mellanox Join Forces

#50

Post by ajdlinux »

manawy wrote: post #36
nickpsecurity wrote: post #32

Earlier quoted context omitted.

"especially when you need to make sure that 30+ year-old code still work like it's the case in HPC" Most code that works on Intel works on AMD. It's rare that it doesn't. The HPC vendor will have low risk on migration + get a bunch of competing accelerators at various price points for their problem. This is quite an incentive to move even if there would be stragglers.

I have no doubt they do, but still... The question is : are the DOD/DOE (or the chinese/european equivalent) going to risk millions for their next supercomputers on a new architecture or prefer good old intel ? Especially when we know that the jump to exascale computation will only be possible if we get rid of the buses and have everything on the same chip (which is one direction taken by Intel). My point is that the…

IBM is already building two new supercomputers for DoE based on Power. (Look up the CORAL Project.)

(disclaimer: I work for IBM, opinions my own)

Post reply on HN