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Moore’s Law Is About to Get Weird (2015)

nautil.us

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Re: Moore’s Law Is About to Get Weird (2015)

#21

Post by pjc50 »

n00b101 wrote: post #12
api wrote: post #7

One thought that isn't on here: Once the process is "mature" and isn't changing every few years, the error rate could be squeezed way down. That would make it practical and economical to make larger chips. There are cooling and power issues too but I'm sure those are solvable. Make way for the 64-bit 128-core 1024gb RAM 12cm^2 SoC? Call it More's Law? Or a BFC? (for Big F'ing Chip?)

>Make way for the 64-bit 128-core 1024gb RAM 8cm^2 SoC This is already happening? Intel Xeon Knights Landing already has an enormous 6.83cm^2 die size. It has 72 "cores," each of which has a 512-bit vector processor. In some sense, you could say that this chip has 9,216 "single precision cores." It also supports up to 384GB DDR4 RAM, which is not far from your 1024GB. The term "core" is becoming vague, as NVIDIA refe…

Asynchronous does not help you on latency at all - it's not the latency of the clock that matters. It's the data latency. This is already kind of crippling, as it takes hundreds of cycles to get anything from RAM if it's not in your cache.

Only way to improve that is to make programming languages push either data locality or dataflow like designs, which may mean giving up or reimagining OO.

Error rates (yield) are a serious problem, but if your design is uniform enough you can very well get away with just disabling bits. There's also a less obvious problem with on-chip variation (OCV) - some physical properties have a gradient across the chip. At runtime, there's a temperature gradient as well.

Re: Moore’s Law Is About to Get Weird (2015)

#22

Post by api »

pjc50 wrote: post #21
n00b101 wrote: post #12

Earlier quoted context omitted.

>Make way for the 64-bit 128-core 1024gb RAM 8cm^2 SoC This is already happening? Intel Xeon Knights Landing already has an enormous 6.83cm^2 die size. It has 72 "cores," each of which has a 512-bit vector processor. In some sense, you could say that this chip has 9,216 "single precision cores." It also supports up to 384GB DDR4 RAM, which is not far from your 1024GB. The term "core" is becoming vague, as NVIDIA refe…

Asynchronous does not help you on latency at all - it's not the latency of the clock that matters. It's the data latency. This is already kind of crippling, as it takes hundreds of cycles to get anything from RAM if it's not in your cache. Only way to improve that is to make programming languages push either data locality or dataflow like designs, which may mean giving up or reimagining OO. Error rates (yield) are a…

Or... continuing with the BFC concept... make chips with monster caches or even with all SRAM running at core speed. That's not been done in a while.

Re: Moore’s Law Is About to Get Weird (2015)

#23

Post by Symmetry »

ansible wrote: post #5

Well, none of those listed technologies is practical. Ternary logic is really cool, but it only gets you about a 10% efficiency improvement. I think it would be awesome to go in this direction, but retooling our entire tech stack for that isn't going to happen. I mean, look at x86. The only thing that will really make progress is molecular nanotechnology. I had always believed that reaching the end of silicon process…

Note that keep referencing Intel, because they've been at the leading edge. AMD doesn't have 14nm in production, for example.

AMD actually just released their first 14 nm products this summer in the form of graphics cards. They don't have any CPUs out in such an advanced process but I think that reflects the architectural cul de sac they've been stuck in. They're next architecture, Zen, is supposed to be 14nm and it doesn't look like it makes business sense to port a Bulldozer derivative to 14nm before Zen is ready.

Re: Moore’s Law Is About to Get Weird (2015)

#24

Post by Symmetry »

pjc50 wrote: post #17
swalsh wrote: post #14

Earlier quoted context omitted.

"retooling our entire tech stack for that isn't going to happen. I mean, look at x86." I wonder if today it's easier than people imagine, but the lessons of Itanium are used as a signal to not try. Sure there are plenty of apps which make low-level use of x86 features, and those probably aren't going to be updated. However a lot of modern software is written in languages that go through interrupters. Java, C#, Python…

Switching to ternary means retooling not just the programming stack but the IC design stack. IC design is actually quite a conservative business, mainly because failures are so expensive. You'd need to spend several years writing a ternary RTL synthesis, place, route and verification suite before starting.

I would expect that once silicon stops shrinking and both chips and fabs can be allowed to pay for themselves over longer time horizons we're going to see a lot more architectural experimentation.

Re: Moore’s Law Is About to Get Weird (2015)

#25

Post by GrumpyYoungMan »

One interesting avenue of research is embedded reconfigurable computing technologies like eMIPS [0]. Unlike other reconfigurable computing approaches that simply place a FPGA side-by-side with a CPU in the same package to act as a co-processor [1], eMIPS integrates reconfigurable logic directly into the processing pipeline, allowing the creation of custom processor instructions on the fly on a per app basis to accelerate apps. Pretty cool stuff.

[0] https://www.microsoft.com/en-us/research/project/emips/

[1] http://www.theregister.co.uk/2016/03/14/intel_xeon_fpga/

Re: Moore’s Law Is About to Get Weird (2015)

#26

Post by pjc50 »

api wrote: post #22
pjc50 wrote: post #21

Earlier quoted context omitted.

Asynchronous does not help you on latency at all - it's not the latency of the clock that matters. It's the data latency. This is already kind of crippling, as it takes hundreds of cycles to get anything from RAM if it's not in your cache. Only way to improve that is to make programming languages push either data locality or dataflow like designs, which may mean giving up or reimagining OO. Error rates (yield) are a…

Or... continuing with the BFC concept... make chips with monster caches or even with all SRAM running at core speed. That's not been done in a while.

Caches effectively are SRAM. It's inherently much less dense than DRAM; I had a quick look on Intel and the largest I could see was 37Mb of cache.

Re: Moore’s Law Is About to Get Weird (2015)

#27

Post by pantalaimon »

swalsh wrote: post #14
ansible wrote: post #5

Well, none of those listed technologies is practical. Ternary logic is really cool, but it only gets you about a 10% efficiency improvement. I think it would be awesome to go in this direction, but retooling our entire tech stack for that isn't going to happen. I mean, look at x86. The only thing that will really make progress is molecular nanotechnology. I had always believed that reaching the end of silicon process…

"retooling our entire tech stack for that isn't going to happen. I mean, look at x86." I wonder if today it's easier than people imagine, but the lessons of Itanium are used as a signal to not try. Sure there are plenty of apps which make low-level use of x86 features, and those probably aren't going to be updated. However a lot of modern software is written in languages that go through interrupters. Java, C#, Python…

What about ARM?

Re: Moore’s Law Is About to Get Weird (2015)

#28

Post by mmmBacon »

Symmetry wrote: post #24
pjc50 wrote: post #17

Earlier quoted context omitted.

Switching to ternary means retooling not just the programming stack but the IC design stack. IC design is actually quite a conservative business, mainly because failures are so expensive. You'd need to spend several years writing a ternary RTL synthesis, place, route and verification suite before starting.

I would expect that once silicon stops shrinking and both chips and fabs can be allowed to pay for themselves over longer time horizons we're going to see a lot more architectural experimentation.

I hope you're right. The costs of 7nm are so high that even the "big guys" are being very careful about what they do. It's become so expensive they just can't afford a miss in the market. I worry the high costs will stifle innovation and that we'll see something that's more like a tweak here and there for a while.

Re: Moore’s Law Is About to Get Weird (2015)

#29

Post by [deleted] »

n00b101 wrote: post #12
api wrote: post #7

One thought that isn't on here: Once the process is "mature" and isn't changing every few years, the error rate could be squeezed way down. That would make it practical and economical to make larger chips. There are cooling and power issues too but I'm sure those are solvable. Make way for the 64-bit 128-core 1024gb RAM 12cm^2 SoC? Call it More's Law? Or a BFC? (for Big F'ing Chip?)

>Make way for the 64-bit 128-core 1024gb RAM 8cm^2 SoC This is already happening? Intel Xeon Knights Landing already has an enormous 6.83cm^2 die size. It has 72 "cores," each of which has a 512-bit vector processor. In some sense, you could say that this chip has 9,216 "single precision cores." It also supports up to 384GB DDR4 RAM, which is not far from your 1024GB. The term "core" is becoming vague, as NVIDIA refe…

[deleted]
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