A 32nm 1000-Processor Array • Hacker News Board

Re: A 32nm 1000-Processor Array

#21

Post by white-flame » Mon, Jun 20, 2016, 8:57 AM UTC

I think that http://venraytechnology.com/ is the only high CPU density design I've seen that seems useful for general purpose, large-footprint computing, but their launch model (sell to a DRAM manufacturer and cash out) didn't go anywhere.

So many of these tons-of-cores chips can't really do much per chip, and are only suited for streaming algorithms like encryption, data packet routing, video stream processing, etc. They also have nowhere near the memory bandwidth to compare to GPUs, or to feed those many processing units with unique data per unit.

Would somebody please think of the memory requirements? :-P (or Venray, please seek investment and start pushing your designs yourself)

Re: A 32nm 1000-Processor Array

#22

Post by rbanffy » Mon, Jun 20, 2016, 9:17 AM UTC

willvarfar wrote: post #4

So how do you program such a beast? What progress is being made on that front? Cache coherency seems really hard to give up on, and even CPU-GPU cache coherency is becoming the expected norm, with even ARM delivering it.

I've read the first paragraphs, so take my comment with a grain of salt.

There are 12 memory modules on the chip, so I assume each is shared by less than 100 cores, which is close to a beefy multithreaded server chip. Each core also has a small local program memory that's not shared between them. It'd be not unlike programming a networked cluster of processing nodes each with a separate chunk of memory, except that the cores could be assigned to neighboring workloads.

Sounds fun!

Re: A 32nm 1000-Processor Array

#23

Post by frozenport » Mon, Jun 20, 2016, 9:27 AM UTC

mrb wrote: post #18

It is surprising the paper makes no comparisons with GPUs. So I will do it. For starters it looks like they are talking about integer operations (I only skimmed the paper and it mentions an ALU, not an FPU), whereas my GPU numbers below are single precision floating point numbers. So it is apples vs oranges. So, a modern 14-16nm GPU like the Tesla P100 or RX 480 does about 5 to 10 trillion ops/sec at 200-300 W, and a…

Cursory Google search shows Pascal GPUs at 10pJ/op for double precision (these guys did int, which should be 10x faster)[1,2]

[1] http://wccftech.com/nvidia-pascal-volta-gpus-sc15/

[2] http://prism.sejong.ac.kr/download/PRISM3_paper/PRISM_Ajayku...

Re: A 32nm 1000-Processor Array

#24

Post by duckingtest » Mon, Jun 20, 2016, 9:35 AM UTC

mrb wrote: post #18

It is surprising the paper makes no comparisons with GPUs. So I will do it. For starters it looks like they are talking about integer operations (I only skimmed the paper and it mentions an ALU, not an FPU), whereas my GPU numbers below are single precision floating point numbers. So it is apples vs oranges. So, a modern 14-16nm GPU like the Tesla P100 or RX 480 does about 5 to 10 trillion ops/sec at 200-300 W, and a…

(Dynamic) Power consumption goes up with square of voltage, so a comparison with a gpu's max power efficiency point (almost certainly underclocked and undervolted) could change the comparison significantly.

Re: A 32nm 1000-Processor Array

#25

Post by kirushik » Mon, Jun 20, 2016, 9:55 AM UTC

foota wrote: post #7

Does anyone have a link or the name of another weird architecture that was posted a while ago? (~3 months maybe?) I remember that there were a large number of cores that all communicated with each other in some weird way and that they like didn't have main system memory or something like that...

Multiclet? https://en.wikipedia.org/wiki/Multiclet

Re: A 32nm 1000-Processor Array

#26

Post by TickleSteve » Mon, Jun 20, 2016, 10:10 AM UTC

RachelF wrote: post #5

willvarfar wrote: post #4

So how do you program such a beast? What progress is being made on that front? Cache coherency seems really hard to give up on, and even CPU-GPU cache coherency is becoming the expected norm, with even ARM delivering it.

It's very hard. In the mid 1980s there was a CPU called a "Transputer" [1] made some of the people who moved to ARM. These CPUs could be connected together in huge networks and directly talk to each other. The network of CPU's could auto-discover its topology, but coding for so many CPU's was difficult. Some specific algorithms scaled well with the number of CPUs, but most did not. [1] https://en.wikipedia.org/wiki/T…

I was involved with a system porting it from an old transputer based system to a PowerPC&C/C++ based one.

Transputers never really scaled into this sort of league, they were more 8/16/32 type scenarios..

For the interested, there was also the Atari Transputer Workstation (ATW).

...Although interesting, they were expensive and didn't perform compared to the equivalent sequential machine. Given development tho, who knows where it could have gone.

Re: A 32nm 1000-Processor Array

#27

Post by chongli » Mon, Jun 20, 2016, 10:22 AM UTC

Would a language like Erlang make sense for a machine like this? Run 1000s of communicating processes without any shared data.

Re: A 32nm 1000-Processor Array

#28

Post by greggman » Mon, Jun 20, 2016, 10:26 AM UTC

I'm certainly hopeful this will lead somewhere useful. Intel tried with Larrabee but apparently couldn't get the perf they wanted, especially with comparisons to GPUs

It would be great to know what the trade-offs are with this architecture

Re: A 32nm 1000-Processor Array

#29

Post by loxs » Mon, Jun 20, 2016, 10:30 AM UTC

chongli wrote: post #27

Would a language like Erlang make sense for a machine like this? Run 1000s of communicating processes without any shared data.

I don't think Erlang's VM is that optimized. Currently (as far as I remember) the upper limit is to run 1024 schedulers (threads) but I imagine it certainly wont be 10x more efficient than running 100 schedulers on 100 core machine

Re: A 32nm 1000-Processor Array

#30

Post by jacquesm » Mon, Jun 20, 2016, 10:32 AM UTC

foota wrote: post #12

jacquesm wrote: post #8

Earlier quoted context omitted.

Sutherlands 'Fleet'?

Doesn't look like it... there was an established website for the project. It seemed to have some big names from processor design and such behind it as well (at least from what I gathered on their wikipedia pages ;) ) For future reference, here is a link talking about the arch mentioned so that no one else has to wade through google's results for "fleet architecture": http://arc.cecs.pdx.edu/publications edit: previou…

That one?:

https://news.ycombinator.com/item?id=11845698