Live data from Hacker News

Intel's roadmap for Optane SSDs with 1,000x performance

computerworld.com

61–70 of 108 posts

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#61
post #27

To be perfectly clear: the 1000x claim isn't about throughput , but latency . The graph in the article makes this clear: spinning drives have latencies on the order of 10ms, NAND flash about 10us, and DRAM about 1ns. The claim is that Optane will achieve latencies on the order of 10ns, or 1000x better than NAND. The on-stage benchmark shows a write throughput of about 2GB/s, which is a much more modest improvement ov…

Consumer OS I/O software stacks are completely unable to deal with this. It was fine for spinning drive latency, it's okay(ish) for high-performance SSD but the open/read/write model just cannot work that fast. It's several orders of magnitude off. Assuming we keep the file system model, I'm guessing some kind of direct memory mapping is in order? Anyone knows what's ahead of us on the software side, to take advantag…

This is a great question. One way I imagine it:

Short term, the disk controller becomes a peripheral on the memory bus. On a 64-bit x86-64 system, the top 16 bits of the address are either 0000 or ffff for RAM. Make it so that the prefix 1000 (for example) maps to the disk, so accessing (physical) address 1000000013371000 accesses byte 13371000 on the disk.

Now processes can just ask the OS to perform a physical memory mapping to obtain a range of virtual addresses directly backed by disk pages, with page protections set based on their filesystem permissions. Such physical address mapping interfaces already exists in most OSes to support memory mapped I/O (for example, mapping /dev/mem in Linux).

This addressing scheme has another advantage: other devices on the system can use e.g. DMA to directly talk to the disk without any CPU intervention. For example, the GPU could load textures straight off of disk, just like John Carmack wants.

Medium term, we start rethinking the filesystem. If we make the address range for a given disk completely persistent, we can just put pointers to disk bytes on the disk itself. Processes will use the same virtual addresses as the physical addresses when talking to the disk. Suddenly "serialization" to disk is no longer required: data structures can be stored in native form directly on the disk. Imagine having a "dmalloc" function call hand you a chunk of persistent storage which you treat the same as any memory, but which can outlive the process. Similar concepts exist in some languages (like MUMPS), and now we bring the idea to all programming environments.

Long term, RAM ceases to be an independent entity, and merely becomes OS-managed cache for the big persistent storage (assuming it still has any latency/bandwidth advantages by this point). Now you can get rid of the notion of "shutting down" or "starting up" the system: everything is persistent. Without having to constantly refresh DRAM to keep the system alive, devices can "sleep/hibernate" more frequently and readily, saving significant power. Programming models become nearly unrecognizable as old models of memory management and process lifetimes give way to new models of persistent storage management and eternal services.

We're not far off from seeing a potential revolution in computing here.

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#62

This will change deeply how we make desktop applications, as well as database management systems.

IBM AS/400 did this decades ago. It has a unified address space - you only see "space" not disk/ram split.

Actually single-level store concept was introduced in Atlas, used in MULTICS, AS/400. [1] Some modern and quite high-performance solutions are using this concept, e.g. LMDB [2]

[1] https://en.wikipedia.org/wiki/Single-level_store [2] https://symas.com/getting-down-and-dirty-with-lmdb-qa-with-s...

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#64

To be perfectly clear: the 1000x claim isn't about throughput , but latency . The graph in the article makes this clear: spinning drives have latencies on the order of 10ms, NAND flash about 10us, and DRAM about 1ns. The claim is that Optane will achieve latencies on the order of 10ns, or 1000x better than NAND. The on-stage benchmark shows a write throughput of about 2GB/s, which is a much more modest improvement ov…

DRAM does not have 1ns latency! On a 4ghz skylake chip you can access the L1 cache at 1ns. DRAM is going to be more in the range of 60(local)-100(remote) nanoseconds. Optane will likely be > 300ns latency from what I've heard, if you access it directly through the CPU memory controller via loads and stores, which is still very impressive.

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#65
post #64

To be perfectly clear: the 1000x claim isn't about throughput , but latency . The graph in the article makes this clear: spinning drives have latencies on the order of 10ms, NAND flash about 10us, and DRAM about 1ns. The claim is that Optane will achieve latencies on the order of 10ns, or 1000x better than NAND. The on-stage benchmark shows a write throughput of about 2GB/s, which is a much more modest improvement ov…

DRAM does not have 1ns latency! On a 4ghz skylake chip you can access the L1 cache at 1ns. DRAM is going to be more in the range of 60(local)-100(remote) nanoseconds. Optane will likely be > 300ns latency from what I've heard, if you access it directly through the CPU memory controller via loads and stores, which is still very impressive.

I'm quoting from the graph in the article. The numbers are also meant to be "on the order of", since the graph only provides that level of detail - so, for example, 1ns really means "1-9ns".

I believe that they are using fairly best-case latency numbers, under the assumption that the memory accesses are close to sequential. For random memory accesses, as you note, the latencies are higher. Unfortunately the article doesn't go into detail on what Optane's worst-case latencies are, nor what the latencies will be like in a real functional system (mostly because Intel has only early prototypes to show).

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#66
post #64

Earlier quoted context omitted.

DRAM does not have 1ns latency! On a 4ghz skylake chip you can access the L1 cache at 1ns. DRAM is going to be more in the range of 60(local)-100(remote) nanoseconds. Optane will likely be > 300ns latency from what I've heard, if you access it directly through the CPU memory controller via loads and stores, which is still very impressive.

I'm quoting from the graph in the article. The numbers are also meant to be "on the order of", since the graph only provides that level of detail - so, for example, 1ns really means "1-9ns". I believe that they are using fairly best-case latency numbers, under the assumption that the memory accesses are close to sequential. For random memory accesses, as you note, the latencies are higher. Unfortunately the article d…

Yeah, I wouldn't do that, that graph is hardly accurate. 9ns won't get you a L3 cache hit on most skylake chips, nevermind main memory.

For sequential access giving a latency number doesn't make sense - you need to talk throughput. You can get upwards of 20gb/s with a single core for DRAM. Here you're at least bounded by the 4x PCI interface (more likely the Optane device) so maybe 3GB/s if you're feeling generous.

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#67

To be perfectly clear: the 1000x claim isn't about throughput , but latency . The graph in the article makes this clear: spinning drives have latencies on the order of 10ms, NAND flash about 10us, and DRAM about 1ns. The claim is that Optane will achieve latencies on the order of 10ns, or 1000x better than NAND. The on-stage benchmark shows a write throughput of about 2GB/s, which is a much more modest improvement ov…

Ok, a couple of things. First, I found it really amazing at how convoluted Intel plotted their numbers on that latency graph so that it would "Up and to the right" which everyone "knows" is good.

The second thing is that Intel has been claiming multiple GB/second of throughput as well. They really do believe this will be a replacement for DRAM on some platforms. As in you read into your L3 case from this stuff and you flush to it when you write out a dirty cache lines. And while that will make the overall system slower, it gives it literally instant stop/start capability if the key parts of your architecture are static (can retain data at 0 clock). What that means is a laptop that can turn it self off between waiting for sectors to read in from the disk or packets to come off the network, or keys to be pressed by the user. Non-illuminated run times in days off of a battery source rather than hours.

Imagine a 1.2TB of this stuff on the motherboard substituting for DRAM. So you've got every application and all the data for your applications already "in memory" as far as the chip is concerned. App switching? Instant, app data availability? instant. Quite a different experience than what we have today.

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#69
post #27

Earlier quoted context omitted.

Consumer OS I/O software stacks are completely unable to deal with this. It was fine for spinning drive latency, it's okay(ish) for high-performance SSD but the open/read/write model just cannot work that fast. It's several orders of magnitude off. Assuming we keep the file system model, I'm guessing some kind of direct memory mapping is in order? Anyone knows what's ahead of us on the software side, to take advantag…

Files exist because persistent storage is slow, copying data from RAM to disk is slow and we'd like to have a way to refer by name to blobs of bytes, but in the end it is only there because it's a useful metaphor. If the metaphor gets in the way of our ability to use the storage medium you can either do a mapping (like the direct memory mapping you refer to), which in this case would almost be like a backwards compat…

This was the original architecture of Multics BTW -- the world just consisted of a single address space of segments (pages) plus a capability-based address space; a higher level construct gave you a named structure for a group of segments.

A similar approach has been taken with HP's interesting memristor-based "Machine"

There's a lot of interesting stuff in Organick's book on Multics, not all of which was implemented, unfortunately. And a lot of really good stuff was tossed overboard when fitting Unix into a PDP-7 (a lot of overwrought bad stuff was jettisoned too -- don't get the wrong idea!).

Re: Intel's roadmap for Optane SSDs with 1,000x performance

#70
No discussion of power in the fluffy article; perhaps there was some in the youtube preso but it's impossible to search or skim that. This would definitely be a game changer if they can really ship it that quickly. It's funny that a SVP talked about notebooks rather than phones or servers, where this could possibly be more effective. That shows where Intel's head is, unfortunately.

I wonder how it compares to the memristor, which also has a sub 90 ns switching time and pretty low power. Optane blows that out of the water, if it's not vaporware.

Post reply on HN