251–260 of 283 posts
I'm happy to hear that this is finally public so I can actually talk about the work I did when I was at Google :-). I'm a bit surprised they announced this, though. When I was there, there was this pervasive attitude that if "we" had some kind of advantage over the outside world, we shouldn't talk about it lest other people get the same idea. To be clear, I think that's pretty bad for the world and I really wished th…
Given the insane mask costs for lower geometries, the ASIC is most likely an Xilinx EasyPath or Altera Hardcopy. Otherwise the amortization of the mask and dev costs -- even for a structured cell ASIC -- over 1K unit wouldn't make much sense versus the extra cooling/power costs for a GPU.
I would suspect they're aiming for orders of magnitudes > 1k units though?
Consider that they will most likely make another version, with new features in 2 years time. I'm sure the users of the chip will want that, just like any other system.
Given the insane mask costs for lower geometries, the ASIC is most likely an Xilinx EasyPath or Altera Hardcopy. Otherwise the amortization of the mask and dev costs -- even for a structured cell ASIC -- over 1K unit wouldn't make much sense versus the extra cooling/power costs for a GPU.
Don't forget shuttle runs. Adepteva used those and otherwise good engineering practice to develop two products, latest in 65nm, with no more than $2mil. This one might be simpler and cheaper given its requirements. http://www.adapteva.com/andreas-blog/a-lean-fabless-semicond...
I'd imagine since they'd want to squeeze every performance per want out of the chip they'd want to go for smallest node possible. Virtex7 EasyPath is 16nm! It is pin to pin compatible with the FPGA version -- because they just change the mask layer and you get it in about 6 weeks. Hard to beat that.
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Don't forget shuttle runs. Adepteva used those and otherwise good engineering practice to develop two products, latest in 65nm, with no more than $2mil. This one might be simpler and cheaper given its requirements. http://www.adapteva.com/andreas-blog/a-lean-fabless-semicond...
True. That's another possibility. I'd imagine since they'd want to squeeze every performance per want out of the chip they'd want to go for smallest node possible. Virtex7 EasyPath is 16nm! It is pin to pin compatible with the FPGA version -- because they just change the mask layer and you get it in about 6 weeks. Hard to beat that.
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True. That's another possibility. I'd imagine since they'd want to squeeze every performance per want out of the chip they'd want to go for smallest node possible. Virtex7 EasyPath is 16nm! It is pin to pin compatible with the FPGA version -- because they just change the mask layer and you get it in about 6 weeks. Hard to beat that.
I didn't know they were still doing EasyPath. And I surely didn't know they did pin-for-pin on 16nm. Holy crap! :)
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> You can make some assumptions though. If the power consumption was equal, the performance is 10x. While I agree some performance per unit increase is likely, how does a direct 10x increased based on power savings follow? Less power usage does not mean that the chip can run through more flops in the same amount of time, right?
It does if power was the limiting factor in clock speed.
http://electronics.stackexchange.com/questions/122050/what-l...
(see graph in the first answer)
Also, it's not known that the TPU have a way to allow to increase the clockspeed arbitrarily, nor is it known whether their architecture is capable of ensuring correctness at arbitrary clock frequencies. Some architectures make assumptions like "The time for this gate to reach saturation is very small compared to the clock frequency, so we'll pretend that it's instantaneous."
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I didn't know they were still doing EasyPath. And I surely didn't know they did pin-for-pin on 16nm. Holy crap! :)
Yes. It is very popular for high-end FPGA use cases. Essentially instead of relying on the built-in routing matrix which makes FPGAs what they are, they modify the metal layer and connect the chip per your design as an ASIC. You get much lower power consumption and much faster clock rates. You also get it in about 6-8 weeks and is guaranteed to match your original design in functionality. It is 100% pin compatible be…
http://www.easic.com/products/28-nm-easic-nextreme-3/
https://www.triadsemi.com/reconfigurable-full-custom-asic/
eASIC has a maskless capability where they straight-up print your silicon for prototyping/testing. Triad brought S-ASIC's to analog/mixed-signal. They're top players. eASIC's basic prototyping was $50k for 50 chips on older ones. Idk now. Triad I heard is $400k flat. Need a price quote to be sure. ;)
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Yes. It is very popular for high-end FPGA use cases. Essentially instead of relying on the built-in routing matrix which makes FPGAs what they are, they modify the metal layer and connect the chip per your design as an ASIC. You get much lower power consumption and much faster clock rates. You also get it in about 6-8 weeks and is guaranteed to match your original design in functionality. It is 100% pin compatible be…
Cool stuff. Previously, I was looking at eASIC or Triad if I needed this cuz I thought FPGA people cancelled S-ASIC's. Good to know there's a high-end one from Xilinx. Here's the others in case you didn't know about them: http://www.easic.com/products/28-nm-easic-nextreme-3/ https://www.triadsemi.com/reconfigurable-full-custom-asic/ eASIC has a maskless capability where they straight-up print your silicon for prototy…
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Wonder what it will do the the industry term Full Stack Developer . Will people who call themselves that will now need to know about chip design? OT: Cool blog! :)
At some point in the past, Rob Pike mentioned that when we was working on Voyager (that spaceship that almost 40 years after launch, has left the solar system and continues to send back valuable science data), he had a relatively good understanding of the system from the quantum level (transistors are based on quantum theory) to the solar system. He wasn't kidding, either.
Then again, I've been coding for ~25 years, am an avid amateur astronomer, and have a degree in physics, so maybe the moral here is that some things just just take more time to master, beyond those first 6 weeks in a coding camp learning how to put together your first jQuery.
:-)
I think the confluence of new technologies, and the re-emergence / rediscovery of older technologies is going to be the best combination. Whether it goes that way is not certain, since the best technology doesn't always win out. Here, though, the money should, since all would greatly reduce time and energy in mining and validating: * Vector processing computers - not von Neumann machines [1]. * Array languages new, o…
I agree with your overall point that we're seeing a confluence of factors. The advances in compiler technology, combined with the vectorial nature of the problems that are interesting to solve in an era of big data, mean that we can achieve a great deal of productivity by using high-level vector-capable languages.