Earlier quoted context omitted.
Most academic shuttle runs are still at 90nm, or bigger. There are a few reasons for this: cost of runs, cost of tooling (hundreds of k), and the fact that your assumptions about transistor action and modeling are exponentially more complicated at advanced process nodes. Academics also sign NDAs about the processes they use, and can only make certain things available; the most open is probably MOSIS, but that's absol…
I'd agree that most runs are at 90nm or above. Yet, the rest is confusing given I have quite a few papers with competitive stuff done at 45-65nm with some at 28 or 32nm. So, why you say forget about it or MOSIS below 90nm if academics are getting working chips done that low?
If you have a few spare million dollars, you still can't necessarily release a lot of data due to the NDAs - usually they give you models for the processes that are proprietary (and they invested a lot in developing, and so will consider any breach an act of war).