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Why I will be using RISC-V in my next chip

adapteva.com

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Re: Why I will be using RISC-V in my next chip

#71

Post by chei0aiV »

krupan wrote: post #52
purpled_haze wrote: post #28

Earlier quoted context omitted.

Even though it isn't GPL anymore, how exactly would it kill all hope?

How does the GPL apply to hardware? Let's say I take some GPL'ed verilog code, modify it a bit, build a chip out of it and sell the chip. Am I required to provide the verilog "source" for my chip? I guess if the chip counts as "object code" in GPL lingo then the answer is yes. There's a lot more than just the verilog code that goes into building a chip though. How is the physical layout, for example, handled? Is that…

Copyright doesn't apply to physical hardware but it probably applies to hardware designs. There are various laws protecting ICs but I'm not sure they allow for copyleft-like hacks.

https://en.wikipedia.org/wiki/Integrated_circuit_layout_desi...

Re: Why I will be using RISC-V in my next chip

#72

Post by userbinator »

FullyFunctional wrote: post #59
userbinator wrote: post #46

I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is such a good idea. Benchmarks are controversial but by most measures the RISC-V performance should be “good enough”…

Market success != technical merit. However, if you're willing to consider ARM a RISC (well, almost) then there's your market success. Alpha completely dominated the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC. At the time, x86 compatibility mattered more than it does today. For people designing their own cores for whatever reason (there can be many, resear…

However, if you're willing to consider ARM a RISC (well, almost) then there's your market success.

ARM wasn't really a pure RISC from the beginning (e.g. multicycle instructions like LDM/STM, pre/post-increment addressing modes, built-in shifts), and I'd say the market success, especially more recently, is attributable to the fact that ARM cores are becoming more x86-like.

On the other hand, MIPS is the quintessential RISC, and hit as enjoyed some success, but was never really known much for amazing performance or efficiency. I suspect RISC-V will be similar, and all the cheap Chinese tablets/phones/etc. that are currently using MIPS may switch to RISC-V instead, although many are unlicensed clones so cost may not be a factor to them.

Alpha completely dominated the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC.

Alphas relied primarily on clock frequency to achieve their performance, and were very power-hungry as a result. This is absolutely the RISC philosophy of performance via simpler designs and increasing clock frequency, which stopped being viable long ago. A 200MHz 21064 can do 0.675DMIPS/MHz and consumes 30W, or 0.0225DMIPS/MHz/W; a Pentium (P5) 100MHz has 1.88DMIPS/MHz and consumes 10W, for 0.188DMIPS/MHz/W.

Re: Why I will be using RISC-V in my next chip

#73

Post by sklogic »

wsxcde wrote: post #66
_yosefk wrote: post #8

Earlier quoted context omitted.

VLIW DSPs are in every phone. VLIW CPUs are almost certainly a bad idea and as to GPUs, AFAIK VLIW needs to coexist with barrel threading there which might create problems. But VLIW certainly has its place.

I suspect the DSP makers just use VLIW because of interia. They probably don't have the money or incentive to revisit their old decisions. Also wouldn't you say that most of the stuff that used to be implemented on DSPs is now moving into ASICs? I wouldn't be so sure that VLIWs are going to be around forever.

VLIW is many times cheaper (in terms of power and area) than OoO. It is not going anywhere from the low budget range.

Re: Why I will be using RISC-V in my next chip

#74

Post by userbinator »

wsxcde wrote: post #63
userbinator wrote: post #46

I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is such a good idea. Benchmarks are controversial but by most measures the RISC-V performance should be “good enough”…

What are you qualifications in computer architecture? You're arguing against pretty much everyone in the field. > I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is…

You seem to be implying that there's RISC failed.

It did fail to deliver on all its promises.

RISC is requires less logic (=area,power) to implement

True, but ultimately it is overall energy usage that is important. A tiny low-power CPU with less performance will take longer to complete a task than a larger faster higher-power one, meaning it consumes more energy. That's what the article I linked to shows.

processors have faster cycle times

That's not necessarily a good thing, as Intel's failed NetBurst microarchitecture shows. Making a CPU with such short delays that it can run at upwards of 10GHz is futile, as power dissipation becomes a huge problem long before that.

In fact, Intel have a few proprietary microcontrollers hidden inside their chipsets and SoCs that were designed post-2005ish and these have RISC architectures.

If you're referring to the ARC4 in the Management Engine, I have a feeling that was chosen for reasons other than being RISC or otherwise.

It is completely absurd to expect a team of 10 or so grad students to compete with them.

I remember it said that RISC would be so simple and performant that such small teams could easily design CPUs which vastly outperform the big CISCs at much lower prices, so I don't think it's that absurd of an expectation.

Re: Why I will be using RISC-V in my next chip

#75

Post by analognoise »

krupan wrote: post #55
nickpsecurity wrote: post #39

Earlier quoted context omitted.

By allowing anyone to knock off the chip without paying back the R&D. There's already a huge market of counterfeits and clones coming out of China for most things you can think of. It's even easier without reverse engineering: hand design to a fab, individual or MPW, then package and sell the chips. Very little of the price of chips you buy is the material or packaging costs. It's mostly R&D recoup, marketing, admini…

"Very little of the price of chips you buy is the material or packaging costs." Are you sure about that? How much markup over material costs is there on most chips?

100% sure - once you have the masks, pumping out chips is cheap, if you do it in volume.

http://www.adapteva.com/andreas-blog/semiconductor-economics...

Re: Why I will be using RISC-V in my next chip

#76

Post by analognoise »

cmrx64 wrote: post #19
dbdjxjcnd wrote: post #2

SIMD and VLIW are the future of microprocessors, and unfortunately it doesn't seem like this ISA will be able to support them.

False. http://hwacha.org/

Interesting project; no updates for a year. I wonder how the project is going?

Re: Why I will be using RISC-V in my next chip

#77

Post by analognoise »

cmrx64 wrote: post #19
dbdjxjcnd wrote: post #2

SIMD and VLIW are the future of microprocessors, and unfortunately it doesn't seem like this ISA will be able to support them.

False. http://hwacha.org/

Interesting project; no updates for a year. I wonder how the project is going?

Re: Why I will be using RISC-V in my next chip

#78

Post by bjconlan »

I think my biggest concern is big blue, I'm sure they will have an eagle eye on this and make sure that as soon as someone accidentally adds support that falls close to one of their patients it will stifle the energy and progress of the community. The further they slide into the abyss the more desperation will drive moves like this... But only time will tell.

Re: Why I will be using RISC-V in my next chip

#79

Post by sagark »

analognoise wrote: post #76
cmrx64 wrote: post #19

Earlier quoted context omitted.

False. http://hwacha.org/

Interesting project; no updates for a year. I wonder how the project is going?

We've recently released a couple of tech reports on Hwacha:

Hwacha Vector-Fetch Architecture Manual: https://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-2...

Hwacha Microarchitecture Manual: https://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-2...

Preliminary Evaluation Results: https://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-2...

M.S. Thesis on Mixed Precision in Hwacha: https://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-2...

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