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Why I will be using RISC-V in my next chip

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Re: Why I will be using RISC-V in my next chip

#51

Post by Marat_Dukhan »

creshal wrote: post #7
dbdjxjcnd wrote: post #2

SIMD and VLIW are the future of microprocessors, and unfortunately it doesn't seem like this ISA will be able to support them.

RISC-V has a vector mode that can be used for SIMD applications. VLIW has been the future since the 80s, and we're still waiting for the magic wonder compilers that can actually spit out efficient VLIW code. Even GPUs have abandoned VLIW (AMD TeraScale) in favour of RISC (Nvidia, AMD GCN).

nVidia Kepler and Maxwell (i.e. the two latest archs ATM) use VLIW instruction encoding

Re: Why I will be using RISC-V in my next chip

#52

Post by krupan »

purpled_haze wrote: post #28
stolsvik wrote: post #20

Earlier quoted context omitted.

GPL License - kills all hope.

Even though it isn't GPL anymore, how exactly would it kill all hope?

How does the GPL apply to hardware? Let's say I take some GPL'ed verilog code, modify it a bit, build a chip out of it and sell the chip. Am I required to provide the verilog "source" for my chip? I guess if the chip counts as "object code" in GPL lingo then the answer is yes. There's a lot more than just the verilog code that goes into building a chip though. How is the physical layout, for example, handled? Is that considered part of the "corresponding source" in GPL lingo?

Re: Why I will be using RISC-V in my next chip

#54

Post by Marat_Dukhan »

e12e wrote: post #50
userbinator wrote: post #46

I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is such a good idea. Benchmarks are controversial but by most measures the RISC-V performance should be “good enough”…

But aren't modern Intel and AMD CPUs internally RISC(-like)? It seems like we have great compilers for CISC targets, and can make great RISC CPUs that process CISC instruction sets really well? Perhaps the issue is that the internals of eg. modern Intel CPUs are locked up at Intel, so the missing step from CISC assembly to efficient RISC is missing (while we've got high-level/C/C++ to CISC covered)?

No they aren't internally RISC. On big Intel & AMD cores "ADD reg, mem" translates to a single uop. On Intel Atom even "ADD mem, reg" translates to a single uop. In fact, it is mostly legacy instructions (e.g. binary-coded decimal arithmetic) that are translated into multiple uops.

Re: Why I will be using RISC-V in my next chip

#55

Post by krupan »

nickpsecurity wrote: post #39
chei0aiV wrote: post #36

Earlier quoted context omitted.

How does the GPL prevent those costs from being recovered?

By allowing anyone to knock off the chip without paying back the R&D. There's already a huge market of counterfeits and clones coming out of China for most things you can think of. It's even easier without reverse engineering: hand design to a fab, individual or MPW, then package and sell the chips. Very little of the price of chips you buy is the material or packaging costs. It's mostly R&D recoup, marketing, admini…

"Very little of the price of chips you buy is the material or packaging costs."

Are you sure about that? How much markup over material costs is there on most chips?

Re: Why I will be using RISC-V in my next chip

#56

Post by microcolonel »

userbinator wrote: post #46

I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is such a good idea. Benchmarks are controversial but by most measures the RISC-V performance should be “good enough”…

The reason they're dancing around the performance figures is because a) synthetic benchmarks like SPEC and CoreMark are of questionable value, and b) They don't have chips in customers' hands quite yet, so they can't be independently reproduced.

If you look at the current results for Rocket and BOOM, you'll find that these microarchitectures seem competitive with Cortex A5/A8 and Cortex A15 respectively at comparable frequencies.

In addition to this, they seem to have some significant amount of space savings on die. Power/performance ratios already seem to be better (likely due in part to smaller die area).

On a power-performance front, a bigger OoO RISC-V could likely be competitive in peak performance to an intel, though you'd have to find a market for that. There has also been a lot of discussion about a real vector machine extension, and that would likely wipe the floor with x86's packed SIMD if done right.

Re: Why I will be using RISC-V in my next chip

#58

Post by wildmusings »

nickpsecurity wrote: post #45
wildmusings wrote: post #41

Earlier quoted context omitted.

Intel has competitors. Why would Intel want to provide its competitors with what must be, at the very least, tens of millions of dollars worth of work?

You have the right idea but it's way more that you think. Intel spends over a billion dollars per quarter on all their tech. https://ycharts.com/companies/INTC/r_and_d_expense I agree R&D on any given bit of HW design is at least tens of millions. Probably more than once per year going back a decade given it's custom and formally verified. Standard cell approximating that would be a fraction of it but still ridiculou…

Yeah, Intel is one of the biggest companies in the world. I was just speculating an absolute floor for just the microcode in particular.

Re: Why I will be using RISC-V in my next chip

#59

Post by FullyFunctional »

userbinator wrote: post #46

I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is such a good idea. Benchmarks are controversial but by most measures the RISC-V performance should be “good enough”…

Market success != technical merit. However, if you're willing to consider ARM a RISC (well, almost) then there's your market success. Alpha completely dominated the performance segment for years, but they fell behind for reasons that has nothing to do with CISC vs. RISC. At the time, x86 compatibility mattered more than it does today.

For people designing their own cores for whatever reason (there can be many, research and commercial), RISC-V is very attractive because of all the reasons already given, but it's obviously not the only option.

RISC-V is carefully designed compromise; it scales down to extremely cheap cores and up to superscalar. Like Alpha before it, extreme attention has been paid to avoid features/choices that would be bad for OoOE implementations. Some examples:

- rs1, rs2, rd fields are always in the same location and all register sources and destinations are explicit (makes decoding faster and you can start fetching/renaming without having decoded)

- there are no branch delay slots

- instructions produce at most a single result

- no condition codes etc (dependencies are explicit)

- the sign-bit for all immediate fields is in a fixed location (cheaper sign-extension)

and so forth.

I'm also a big fan of the conditional branch instruction which unlike the Alpha can compare two registers.

Re: Why I will be using RISC-V in my next chip

#60

Post by yuhong »

userbinator wrote: post #46

I'm surprised to see a lot of RISC proponents still around, because I think it's quite clear that things didn't quite work out the way they thought it would --- the vision of cheap, simple, high-performance CPUs just didn't happen. Thus I'm not of the opinion that another "MIPS, but free" architecture is such a good idea. Benchmarks are controversial but by most measures the RISC-V performance should be “good enough”…

Thinking about it, it is probably not difficult to create a x86 subset that is user mode compatible with most modern programs but lacks things like segmentation.
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