Can RISC-V be implemented in the on-board Xilinx Zynq 7020 FPGA of the A101040 (Epiphany III) Parallella?
Why I will be using RISC-V in my next chip
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Re: Why I will be using RISC-V in my next chip
#12Can RISC-V be implemented in the on-board Xilinx Zynq 7020 FPGA of the A101040 (Epiphany III) Parallella?
Definitely! Straightforward, especially if you use https://github.com/parallella/oh
Re: Why I will be using RISC-V in my next chip
#13Can RISC-V be implemented in the on-board Xilinx Zynq 7020 FPGA of the A101040 (Epiphany III) Parallella?
Yes, definitely. Berkeley's open-source Rocket[1] core can already be programmed onto the Zedboard and ZC706[2], which also use Zynq 7000 series FPGAs. Getting it to work on the Parallela should just be a matter of changing the clock constraints and pin settings and finding a configuration that will fit on the FPGA.
[1] https://github.com/ucb-bar/rocket-chip [2] https://github.com/ucb-bar/fpga-zynq
Re: Why I will be using RISC-V in my next chip
#14Earlier quoted context omitted.
RISC-V has a vector mode that can be used for SIMD applications. VLIW has been the future since the 80s, and we're still waiting for the magic wonder compilers that can actually spit out efficient VLIW code. Even GPUs have abandoned VLIW (AMD TeraScale) in favour of RISC (Nvidia, AMD GCN).
VLIW DSPs are in every phone. VLIW CPUs are almost certainly a bad idea and as to GPUs, AFAIK VLIW needs to coexist with barrel threading there which might create problems. But VLIW certainly has its place.
In DSPs, sure, but not in general-purpose CPUs or GPUs.
Re: Why I will be using RISC-V in my next chip
#15Earlier quoted context omitted.
RISC-V has a vector mode that can be used for SIMD applications. VLIW has been the future since the 80s, and we're still waiting for the magic wonder compilers that can actually spit out efficient VLIW code. Even GPUs have abandoned VLIW (AMD TeraScale) in favour of RISC (Nvidia, AMD GCN).
VLIW DSPs are in every phone. VLIW CPUs are almost certainly a bad idea and as to GPUs, AFAIK VLIW needs to coexist with barrel threading there which might create problems. But VLIW certainly has its place.
Most DSP archs came out of thr 90's and many of the cores today are a reflection of that trend (ceva etc). I worked on the TigerSharc DSP for 8 years and can tell you that from an implementation standpoint they can be a nightmare! Not sure they do have a viable place long term from an economical perspective.
Re: Why I will be using RISC-V in my next chip
#16How does RISC-V get around the issue of patent mine fields? For example we've seen its really difficult to make a competitive codec without infringing and even when it's accomplished there is lingering doubt until it's challenged. I hope this situation is somehow much different.
Re: Why I will be using RISC-V in my next chip
#17How does RISC-V get around the issue of patent mine fields? For example we've seen its really difficult to make a competitive codec without infringing and even when it's accomplished there is lingering doubt until it's challenged. I hope this situation is somehow much different.
This is why they have a RISC-V foundation, made up of big and small companies (Google, Oracle, HPE, etc.). Most (all?) of the RISC-V ISA is stuff that is out of patent and has a lineage going back more than 20 years. This issue is definitely important and it's not being ignored!
Re: Why I will be using RISC-V in my next chip
#18Can RISC-V be implemented in the on-board Xilinx Zynq 7020 FPGA of the A101040 (Epiphany III) Parallella?
Yes, definitely. Berkeley's open-source Rocket[1] core can already be programmed onto the Zedboard and ZC706[2], which also use Zynq 7000 series FPGAs. Getting it to work on the Parallela should just be a matter of changing the clock constraints and pin settings and finding a configuration that will fit on the FPGA. [1] https://github.com/ucb-bar/rocket-chip [2] https://github.com/ucb-bar/fpga-zynq
not to mention the smaller implementations like picorv32 and zscale/vscale.
Re: Why I will be using RISC-V in my next chip
#19SIMD and VLIW are the future of microprocessors, and unfortunately it doesn't seem like this ISA will be able to support them.
False. http://hwacha.org/
Re: Why I will be using RISC-V in my next chip
#20Good that they're getting on the bandwagon as they're already popular with maker types. I also like the serendipity where this post led me to an equally exciting one: http://www.adapteva.com/announcements/an-open-source-8gbps-l... Love that they developed and open-sourced a 8Gbps, 1us, I/O interface. That might come in handy. :)
GPL License - kills all hope.