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Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

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Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#11

Post by h1290799 »

nkurz wrote: post #2

I try to refrain from purely negative commentary on articles, but yuck! How can one hope to say anything useful about "memory performance" without once using the terms "latency" or "bandwidth"? Memory performance is getting higher in the same way that processor performance is going up: http://www.corsair.com/en-us/blog/2015/september/ddr3_vs_ddr... Latency is to frequency as bandwidth is to parallelism. Single core C…

There is nothing hard about this. You either have a "problem" that can take advantage of multiple cores or sequential reading from memory or you don't. The only way to avoid this is to change the "problem"

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#13

Post by Symmetry »

advancedprivacy wrote: post #4

Moore's Law is about transistor count. Not about frequency, bandwidth or "speed"... Is everybody ignoring this fact?

Moore's 1965 paper was about transistor count doubling every 12 months rather than frequency but "Moore's Law" didn't come into use as a term until 1975, by which time Moore was giving shrinking feature sizes equal billing[1]. And Moore himself wrote a memo endorsing a more general use of the term "Moore's Law" for any chip performance metric that doubles regularly. I can't find a copy online but I have it in my old Computer Architecture lecture notes. And performance and scaling were identical as long as Dennard scaling[2] lasted.

[1]http://www.eng.auburn.edu/~agrawvd/COURSE/E7770_Spr07/READ/G...

[2]https://en.wikipedia.org/wiki/Dennard_scaling

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#14

Post by Symmetry »

When you're talking about memory performance you always have to include the latency, the bandwidth, and the size of the memory pool. 64kb memory pools have scaled in latency and bandwidth at the same rate as processing power - now they're sitting deep in the heart of the chip as the L1 cache.

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#15

Post by oldmanjay »

I'm not certain who this article is targeting, but it reminds of an acquaintance who would ask me detailed technical questions, misunderstand all my answers, and then two days later misinform me of the things I told him as if he were teaching me.

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#16

Post by anonmeow »

Server CPUs have >2x memory channels when compared to consumer CPUs. IBM Power CPUs show that it's possible to get even more memory bandwidth than in mainstream Xeons. Looks like low RAM bandwidth in consumer CPUs is a mostly artificial differentiator to discourage use of these parts in servers.

On the other hand there are HMC and HBM technologies that offer order of magnitude more bandwidth and several times less latency. They are already used in AMD gpus as well as in prototypes of Nvidia's pascal gpu and Intel's Knight's corner 60-core cpu http://www.theplatform.net/2015/03/25/more-knights-landing-x...

I hope HBM comes to consumer CPUs too, but with current lack of competition in the market it can take a long time.

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#17

Post by MichaelGG »

h1290799 wrote: post #11
nkurz wrote: post #2

I try to refrain from purely negative commentary on articles, but yuck! How can one hope to say anything useful about "memory performance" without once using the terms "latency" or "bandwidth"? Memory performance is getting higher in the same way that processor performance is going up: http://www.corsair.com/en-us/blog/2015/september/ddr3_vs_ddr... Latency is to frequency as bandwidth is to parallelism. Single core C…

There is nothing hard about this. You either have a "problem" that can take advantage of multiple cores or sequential reading from memory or you don't. The only way to avoid this is to change the "problem"

Many times you'll have code that doesn't take advantage of multiple chores and sequential memory, but could. Redesigning it is what's hard.

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#18

Post by graycat »

Okay, do the usual: Add microcode to the processor cores to support more capable instructions so that can trigger a streams of all the data with nearly no time for addressing.

E.g., implement heap sift, heap sort, heap priority queue, substring search, of course, inner product accumulation, and whatever else looks promising, e.g., standard multi-dimensional array addressing, chasing down chains of pointers common in OO programming.

That is, have the machine instructions do larger chunks of work.

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#19

Post by nkurz »

graycat wrote: post #18

Okay, do the usual: Add microcode to the processor cores to support more capable instructions so that can trigger a streams of all the data with nearly no time for addressing. E.g., implement heap sift, heap sort, heap priority queue, substring search, of course, inner product accumulation, and whatever else looks promising, e.g., standard multi-dimensional array addressing, chasing down chains of pointers common in…

I'm guessing this is downvoted because it's no longer a viable solution. Microcode generates multiple µops with a single instruction, but the decoded µop cache is large enough (and efficient enough) that the decoding is almost never the bottleneck.

Worse, for anything in a loop it often actually slows things down by preventing the usual caching mechanisms from working. The instructions/µops are already where they need to be, but data dependencies prevent them from being executed in a timely manner.

What's needed instead are changes to the algorithms that allow for more instruction level parallelism. We need to overcome latency by creating assembly lines within the core rather than having each core do piece work.

Re: Memory Is Holding Up the Moore's Law Progression of Processing Power (2014)

#20

Post by ghshephard »

nkurz wrote: post #2

I try to refrain from purely negative commentary on articles, but yuck! How can one hope to say anything useful about "memory performance" without once using the terms "latency" or "bandwidth"? Memory performance is getting higher in the same way that processor performance is going up: http://www.corsair.com/en-us/blog/2015/september/ddr3_vs_ddr... Latency is to frequency as bandwidth is to parallelism. Single core C…

Just as a side note - after working at an RF Networking company for 10+ years, the phrase "bandwidth" (which in RF, is literally the "width of the band", e.g. 200 kHz ) is endlessly confusing, particularly when you hear engineers use phrases like, "we've got more bandwidth resulting in greater range but lower data rate with this signaling scheme."

The RF PHY/MAC engineers use data rate, and bandwidth 100% consistently, and everyone else I've ever met, uses "bandwidth" as a synonym for "data rate" - I'm surprised there isn't more confusion between the two groups of people.

At least all groups measures data rate and "bandwidth" with megabits/sec == 1x10e6 bits/second. Thankfully that confusion never entered the data comms world.

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