Apple facing huge chip patent bill after losing case

Post by sitkack » Wed, Oct 14, 2015, 2:10 PM UTC

matthewmacleod wrote: post #26

masklinn wrote: post #13

Earlier quoted context omitted.

There were branch-predicting mainframes back in the 80s, though it really came to the fore with the advent of superscalar microprocessors in the early 90s (MIPS R8000 and DEC Alpha 21064), what is the paper's innovations above these?

It's pretty clear from even a cursory look – the patent covers a second level of branch prediction, where the processor determines whether or not it should bother speculatively executing an instruction based on the previous outcome of that speculative execution. Whether or not there was a prior implementation of this, I don't know – but it's also obviously more than a simple saturating counter branch predictor or wha…

Post by danbee » Wed, Oct 14, 2015, 2:13 PM UTC

galilyou498 wrote: post #39

propter_hoc wrote: post #38

This is sort of a depressing precedent. Do we really want to turn our universities into patent trolls?

If they are trolling other patent trolls, then why not?

Post by roc » Wed, Oct 14, 2015, 2:21 PM UTC

devit wrote: post #21

Looks like the "idea" of the patent in the description is to use a predictor to predict when a STORE and LOAD alias and not speculate the LOAD and any instruction depending on the load (although the claims generalize this to any non-static dependency). As it generally happens in software/hardware patents, the claimed solution seems quite obvious whenever one wants to solve that particular problem, and the hard part i…

Post by [deleted] » Wed, Oct 14, 2015, 2:30 PM UTC

mzs wrote: post #41

rayiner wrote: post #29

This PDF explains what I discuss below in more detail: http://moodle.technion.ac.il/pluginfile.php/315285/mod_resou... . Prediction of aliasing is discussed on slide 25. The patent in question pertains to an optimization of what these days you'd call "memory disambiguation." In a processor executing instructions out of order, data dependencies can be known or ambiguous. A known data dependency is, for example, summin…

Alpha 21264 (also from '96) had load store buffers that would notice the dependence violations and flush the pipeline during speculative execution. Sparc and power also had this to some extent with write buffers. I can't think of any that used a predictor though to decide whether to execute speculatively or not back then, they all just either did or stalled on the first potential violation. The patent appears novel f…

Post by Tloewald » Wed, Oct 14, 2015, 2:33 PM UTC

roc wrote: post #46

devit wrote: post #21

Looks like the "idea" of the patent in the description is to use a predictor to predict when a STORE and LOAD alias and not speculate the LOAD and any instruction depending on the load (although the claims generalize this to any non-static dependency). As it generally happens in software/hardware patents, the claimed solution seems quite obvious whenever one wants to solve that particular problem, and the hard part i…

Luckily, patents aren't granted for ideas, but for specific executions. Granted, the execution is generally defined at a higher level than, say, "this exact chunk of silicon". But it's at a much lower level than the "idea".