Viewing profile — rosscomputerguy

Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11

Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11

I've definitely had a thought about doing a hard core RISC-V SoC on a dev board.

Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my wa…

You can already port over a RISC-V SoC to Aegis. I have not tested that yet but it is something I really want to do.

Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside…

Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough firs…