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pocak

HN member
Joined
Wed, Apr 25, 2018, 12:10 AM UTC
HN karma
29
Public activity
17 items

About pocak

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Recent public activity

  1. comment
    Comment #43019788

    There is, it's Druid. Intel announced the first four codenames in 2021. > [...] first generation, based on the Xe HPG microarchitecture, codenamed Alchemist (formerly known as DG2)…

  2. comment
    Comment #39844408

    In the post about the texture unit, that ROM table for mip level address offsets seems to use quite a bit of space. Have you considered making the mip base addresses a part of the …

  3. comment
    Comment #31371871

    Right, I had the article's bunny test program on my mind, which looks like it has only one pass. In OpenGL, the driver would have to scan the following commands to see if it can di…

  4. comment
    Comment #31369749

    I don't understand why the programs are the same. The partial render store program has to write out both the color and the depth buffer, while the final render store should only wr…

  5. comment
    Comment #31369499

    That's what I thought, too, until I saw ARM's Hot Chips 2016 slides. Page 24 shows that they write transformed positions to RAM, and later write varyings to RAM. That's for Bifrost…

  6. comment
    Comment #26939951

    In the article, cost is cpu time, and benefit is file size reduction multiplied by number of times watched.

  7. comment
    Comment #25704581

    Linux allocates page tables lazily, and fills them lazily. The only upfront work is to mark the virtual address range as valid and associated with the file. I'd expect mapping gian…

  8. comment
    Comment #23903255

    Only one row at a time has voltage applied to it. In one update, the image is scanned out multiple times, so it appears as if all pixels were changing simultaneously (and perhaps t…

  9. comment
    Comment #23549027

    Took me a while to get past the home screen. I kept clicking 'paint' at the bottom and 'no' at the top.

  10. comment
    Comment #23482681

    Thread migration only costs on the order of 100 microseconds, including the effect of cold caches. If you keep the AVX thread on the big core for at least 100 milliseconds at a tim…

  11. comment
    Comment #23482615

    Migrate back to the little core if the thread hasn't used AVX in a while. Linux already tracks how long ago a task used AVX-512. I assume the same mechanism could be used to track …

  12. comment
    Comment #22776891

    It works by applying a low-pass filter on the camera's motion, so a sudden kick turns into a slow, low amplitude bob. Perhaps you just need to increase the smoothing parameter. I f…

  13. comment
    Comment #17392101

    If you give two threads on one core to one VM, the VM could attack the hypervisor. It could have one thread run the TLB probe loop while the other does something that's handled by …

  14. comment
    Comment #17391947

    Are newer Ryzen 1000 series CPUs still made with the B1 die? I thought steppings were for fixing errata, and once a new revision is qualified, the old one is no longer manufactured…

  15. comment
    Comment #17381962

    There's a nine digit number in the middle of the normal URL. You can take a text-only URL and replace the identifier at the end. Shame on them for not making all articles reachable…

  16. comment
  17. comment
    Comment #16918053

    If your chips aren't very large, you can fit multiple copies in the reticle. E.g., if the litho machine has a 40mm by 50mm reticle, and you're making a 10mm by 10mm die, you can ex…