Viewing profile — cfelton

This is useless without any data: "big difference between the generated verilog". You would need an actual case study to confidently state these and as pointed out with programming…

That is very dangerous not verifying, in some means, that each of the formats are functionally identical. One could skip the Cosimulation in MyHDL as well. This has nothing to do w…

Here is some information on the speed of MyHDL, http://www.myhdl.org/documentation/performance.html . Converting to yet another format can be a pain and potentially dangerous, if y…

This is ridiculous, you can create cycle accurate (and bit accurate) descriptions in MyHDL. Anyone can verify this themselves by creating an RTL description in MyHDL, convert it to…