Viewing profile — bisrig

For some reason, my first thought when I saw this was to think back to this other recent post: https://www.scottsmitelli.com/articles/ideal-candidate/ I feel like these are linked …

I'm not sure what the current state of the art is, but for the longest time it was pretty common for USB peripheral ICs to have small flash devices attached to them in order to be …

Back in the bad old days of version control (thinking of VSS here), I was overall pretty satisfied with how the check-in/check-out mechanics worked for Word docs and the like. In t…

Agree completely. I think Vanguard's UI is trying to send the message "if you're logging in you're doing it wrong".

Hi all, I'm curious as to whether anyone is aware of any trade studies or articles published regarding industry trends for how much money companies spend on a yearly basis for deve…

The StateMover concept sounds pretty interesting and is almost like the reverse of the integrated-logic-analyzer approach that the major vendors have adopted in their tooling. I as…

I don't think that long lines scaled particularly well with increasing number of LUTs and clock rates. All the black magic voodoo that goes into matching prop delay for resources l…

Something that I think is missing in the discussion here with regard to payment methods is: know your market segmentation. If you are targeting b2B (i.e. large business), there are…

Am I reading this right that the standard remote ID broadcast is specified as "something in an unlicensed band, everything else about it you figure it out"? Isn't the point of this…

I know that this doesn't directly address the question you're asking, but to give an idea of the order of magnitude of the effect: the Doppler shift in frequency rounds to f_carrie…

As an aside: it looks like the timing diagrams in this article were created with a tool called WaveDrom. I've used this tool in the past and been impressed with what it's able to d…

I have been through a similar process myself a couple years back, and just wanted to say that this is a really good effort in trying to tame a beast that doesn't really want to be …

I think the heart of what the article is getting at is represented well by the following quote: "To let GPUs blossom into the data-parallel accelerators they are today, people had …

And when Haversine isn't accurate enough: Vincenty's method. https://en.wikipedia.org/wiki/Vincenty%27s_formulae Also, another reference for both methods with calculators! Vicenty:…

Day trading has a specific definition in this context (can't remember if it's SEC, FINRA, or some other acronym), and refers to the buying and selling of the same security with a s…

I spent a few minutes poking around their project scripts, and it looks like that the design file you upload back to EC2 is a post-routed design checkpoint, which is an interesting…

I think the parent comment to yours (or at least the edited version) is right, they are almost surely XCVU9Ps based on the logic element and DSP counts. The ram numbers listed in t…

To add to this - a lot (maybe all?) of the functionality that is described by the concept of "overlays" maps to the design and implementation of the programmable logic in a coproce…

I would be careful of trivializing the last point that you made. Things like extremely long design cycles, environmental requirements, expectations of value-add engineering service…

In addition to the procedural issues already addressed, let me point out that airspace systems are extremely complicated from types of users, given the mix of commercial, GA and mi…

I think the author got a bit confused, as the next paragraph (quoting the VATSIM ATC) clarifies this statement... in the example given the ATC instruction requires readback. "Roger…

A couple of general ideas to help you scope the solution space: - If you can do something with the part still in-circuit (i.e. the PCB assembly itself is still functioning), that's…

I will never forgive the Verilog powers that be for allowing the 'reg' keyword to describe "things that are not registers". But joking aside, the differences between VHDL and Veril…

My best advice: synthesize early and often, and spend the time to poke around in the synthesis schematic viewer - Webpack still includes this I believe. It's a great way to compare…

Having been through SYR recently - the doors are pretty annoying. When I was there, they had a bunch of signs telling people to go through in groups, which was hilarious as 1) the …